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AD9879

SIGMA-DELTA OUTPUTS

The AD9879 contains an on-chip sigma-delta output that pro-

vides a digital logic bit stream with an average duty cycle that

varies between 0% and (4095/4096)%, depending on the pro-

grammed code, as shown in Figure 5.

000h

001h

002h

800h

FFFh

tMCLK

4096

tMCLK

4096

tMCLK

Figure 5. Sigma-Delta Output Signals

This bit stream can be low-pass filtered to generate a program-

mable dc voltage of:

VDC = (Sigma-Delta Code/4096)(VH) + VL

where:

VH = VDRVDD – 0.6 V

VL = 0.4 V

In cable modem set-top box applications, the output can be

used to control external variable gain amplifiers or RF tuners. A

simple single-pole RC low-pass filter provides sufficient filtering

(see Figure 6).

AD9879

MCLK

DAC

CONTROL

WORD

DC(VL TO VH)

TYPICAL: R = 50k

C = 0.1 F

f–3dB = 1/(2 RC) = 318Hz

Figure 6. Sigma-Delta RC Filter

In more demanding applications where additional gain, level

shift, or drive capability is required, a first or second order active

filter might be considered for each sigma-delta output (see Figure 7).

AD9879

SIGMA-DELTA

VSD

VOUT

VOFFSET

VOUT = (VSD + VOFFSET) (1 + R/R1)/2

TYPICAL: R = 50k

C = 0.1 F

f–3dB = 1/(2 RC) = 318Hz

OP250

Figure 7. Sigma-Delta Active Filter with Gain and Offset

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9879 serial port is a flexible, synchronous serial commu-

nications port that allows easy interface to many industry-standard

microcontrollers and microprocessors. The interface allows

read/write access to all registers that configure the AD9879.

Single or multiple byte transfers are supported. Also, the interface

can be programmed to read words either MSB first or LSB first.

The AD9879’s serial interface port I/O can be configured to

have one bidirectional I/O (SDIO) pin or two unidirectional I/O

(SDIO/SDO) pins.

General Operation of the Serial Interface

There are two phases to a communication cycle with the AD9879.

Phase 1 is the instruction cycle, which is the writing of an

instruction byte into the AD9879, coincident with the first eight

SCLK rising edges. The instruction byte provides the AD9879

serial port controller with information regarding the data trans-

fer cycle, which is Phase 2 of the communication cycle. The

Phase 1 instruction byte defines whether the upcoming data

transfer is read or write, the number of bytes in the data transfer,

and the starting register address for the first byte of the data

transfer. The first eight SCLK rising edges of each communication

cycle are used to write the instruction byte into the AD9879.

The eight remaining SCLK edges are for Phase 2 of the communi-

cation cycle. Phase 2 is the actual data transfer between the

AD9879 and the system controller. Phase 2 of the communication

cycle is a transfer of 1 to 4 data bytes as determined by the

instruction byte. Normally, using one multibyte transfer is the

preferred method. However, single byte data transfers are useful

to reduce CPU overhead when register access requires one byte

only. Registers change immediately upon writing to the last bit

of each transfer byte.

Instruction Byte

The instruction byte contains the following information as

shown below:

MSB

LSB

R/W N1

The R/W bit of the instruction byte determines whether a read

or a write data transfer will occur after the instruction byte

write. Logic high indicates a read operation. Logic zero indi-

cates a write operation. The N1:N0 bits determine the number

of bytes to be transferred during the data transfer cycle. The bit

decodes are shown in Table VI.

Table VI.

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

The Bits A4:A0 determine which register is accessed during the

data transfer portion of the communications cycle. For multibyte

transfers, this address is the starting byte address. The remaining

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