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AD9879

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RECEIVE PATH (Rx)

IF10 and IF12 ADC Operation

The IF10 and IF12 ADCs have a common architecture and

share many of the same characteristics from an applications

standpoint. Most of the information in the section below will be

applicable to both IF ADCs. Differences, where they exist, will

be highlighted.

Input Signal Range and Digital Output Codes

The IF ADCs have differential analog inputs labelled IF+ and

IF–. The signal input, VAIN, is the voltage difference between

the two input pins, VAIN = VIF+ – VIF–. The full-scale input

voltage range is determined by the internal reference voltages,

REFT and REFB, which define the top and bottom of the scale.

The peak input voltage to the ADC is the difference between

REFT and REFB which is 1 VPD. This results in the ADC full-

scale input voltage range of 2 VPPD. The digital output code is

straight binary and is illustrated in Table VIII.

Table VIII.

IF[11:0]

Input Signal Voltage

111...111

VAIN >= +1.0 V

111...111

VAIN = +1.0 – (1 LSB) V

111...110

VAIN = +1.0 – (2 LSB) V

...

100...001

VAIN = +1 LSB V

100...000

VAIN = 0.0 V

011...111

VAIN = –1 LSB V

...

000...001

VAIN = –1.0 + (2 LSB) V

000...000

VAIN = –1.0 V

000...000

VAIN < –1.0 V

The IF10 ADC digital output code occupies the 10 most signifi-

cant bits of the Rx digital output port (IF[11:2]). The output

codes clamp to the top or the bottom of the scale when the inputs

are overdriven.

Driving the Input

The IF ADCs have differential switched capacitor sample-and-

hold amplifier (SHA) inputs. The nominal differential input

impedance is 4.0 k

Ω||3 pF. This impedance can be used as the

effective termination impedance when calculating filter transfer

characteristics and voltage signal attenuation from non-zero

source impedances. It should be noted however that for best

performance additional requirements must be met by the signal

source. The SHA has input capacitors that must be recharged

each time the input is sampled. This results in a dynamic input

current at the device input. This demands that the source has

low (<50 V) output impedance at frequencies up to the ADC

sampling frequency. Also, the source must have settling to better

than 0.1% in <1/2 ADC CLK period.

Another consideration for getting the best performance from the

ADC inputs is the dc biasing of the input signal. Ideally, the

signal should be biased to a dc level equal to the midpoint of the

ADC reference voltages, REFT12 and REFB12. Nominally, this

level will be 1.2 V. When ac-coupled, the ADC inputs will self-

bias to this voltage and requires no additional input circuitry.

Figure 20 illustrates a recommended circuit that eases the burden

on the signal source by isolating its output from the ADC input.

The 33

Ω series termination resistors isolate the amplifier outputs

from any capacitive load, which typically improves settling time.

The series capacitors provide ac signal coupling which ensures

that the ADC inputs operate at the optimal dc bias voltage. The

shunt capacitor sources the dynamic currents required to charge

the SHA input capacitors, removing this requirement from the

ADC buffer. The values of CC and CS should be calculated to

get the correct HPF and LPF corner frequencies.

tEE

tMD

tOD

MCLK

RxSYNC

RxIQ

DATA

I[7:4]

I[3:0]

I[7:4]

I[3:0]

Q[7:4]

Q[3:0]

IF10

IF12

IF10

IF12

IF10

IF12

REFCLK

IF DATA

M = 8

Figure 18. Rx Port Timing

(Default Mode: Multiplexed IF ADC Data)

tEE

tMD

tOD

MCLK

RxSYNC

RxIQ

DATA

I[7:4]

I[3:0]

I[7:4]

I[3:0]

Q[7:4]

Q[3:0]

IF10 OR IF12

REFCLK

IF DATA

IF10 OR IF12

M = 8

Figure 19. Rx Port Timing (Nonmultiplexed Data)

AINP

AINN

Figure 20. Simple ADC Drive Configuration

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