AD9879 datasheet(2/24 Pages) AD

2 / 24 page

REV. 0

–2–

AD9879–SPECIFICATIONS

Test

Parameter

Temp

Level

Min

Typ

Max

Unit

OSCIN AND XTAL CHARACTERISTICS

Frequency Range

Full

MHz

Duty Cycle

Full

Input Impedance

25ºC

III

100||3M

Ω||pF

MCLK Cycle to Cycle Jitter

25ºC

III

ps rms

Tx DAC CHARACTERISTICS

Resolution

N/A

Bits

Maximum Sample Rate

Full

232

MHz

Full-Scale Output Current

Full

Gain Error (Using Internal Reference)

Full

–2.0

–1.0

+2.0

%FS

Offset Error

25ºC

III

±1.0

%FS

Reference Voltage (REFIO Level)

25ºC

III

1.23

Differential Nonlinearity (DNL)

25ºC

III

±2.5

LSB

Integral Nonlinearity (INL)

25ºC

III

±8

LSB

Output Capacitance

25ºC

III

Phase Noise @ 1 kHz Offset, 42 MHz

Crystal and OSCIN Multiplier Enabled at 16

25ºC

III

–110

dBc/Hz

Output Voltage Compliance Range

Full

–0.5

+1.5

Wideband SFDR

5 MHz Analog Out, IOUT = 10 mA

Full

60.8

66.9

dBc

65 MHz Analog Out, IOUT = 10 mA

Full

44.0

46.2

dBc

Narrow-band SFDR (

±1 MHz Window):

5 MHz Analog Out, IOUT = 10 mA

Full

65.4

72.3

dBc

Tx MODULATOR CHARACTERISTICS

I/Q Offset

Full

Pass-Band Amplitude Ripple (f < fIQCLK/8)

Full

±0.1

Pass-Band Amplitude Ripple (f < fIQCLK/4)

Full

±0.5

Stop-Band Response (f > fIQCLK

3/4)

Full

–63

Tx GAIN CONTROL

Gain Step Size

25ºC

III

0.5

Gain Step Error

25ºC

III

<0.05

Settling Time to 1% (Full-Scale Step)

25ºC

III

1.8

IQ ADC CHARACTERISTICS

Resolution

N/A

Bits

Maximum Conversion Rate

Full

III

14.5

MHz

Pipeline Delay

N/A

3.5

ADC Cycles

Offset Matching between I and Q ADCs

±4.0

LSBs

Gain Matching between I and Q ADCs

±2.0

LSBs

Analog Input

Input Voltage Range

Full

III

Vppd

Input Capacitance

25ºC

III

2.0

Differential Input Resistance

25ºC

III

Ω

AC Performance (AIN = 0.5 dBFS, fIN = 5 MHz)

Effective Number of Bits (ENOB)

Full

5.25

5.8

Bits

Signal-to-Noise Ratio (SNR)

Full

36.5

Total Harmonic Distortion (THD)

Full

–50

Spurious-Free Dynamic Range (SFDR)

Full

(VAS = 3.3 V

5%, VDS = 3.3 V

10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz,

fMCLK = 54 MHz (M = 8), ADC Clock from OSCIN, RSET = 4.02 k , 75

DAC Load)

*IQ ADC in Default Mode. ADC Clock Select Register 8, Bit 3 set to “0.”

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