LPC55S2X datasheet(57/140 Pages) NXP

57 / 140 page

LPC55S2x/LPC552x

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Product data sheet

Rev. 2.2 — 8 December 2022

57 of 139

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• While USB is in the Suspend mode, the LPC55S2x/LPC552x can enter deep-sleep

mode and wake up on USB activity.

• Double buffer implementation for Bulk and Isochronous endpoints

7.23.2.2 USB1 host controller

The host controller enables high speed data exchange with USB devices attached to the

bus. It consists of register interface and serial interface engine. The register interface

complies with the Enhanced Host Controller Interface (EHCI) specification

Features

• EHCI compliant.

• Two downstream ports.

• Supports per-port power switching.

7.23.3 Flexcomm Interface serial communication

Each Flexcomm Interface provides a choice of peripheral functions, one of which must be

chosen by the user before the function can be configured and used.

7.23.3.1 Features

• USART with asynchronous operation or synchronous master or slave operation.

• SPI master or slave with up to 4 slave selects.

• I2C, including separate master, slave, and monitor functions.

• Flexcomm interfaces 0 to 7 each provide one channel pair of I2S.

• Data for USART, SPI, and I2S traffic uses the Flexcomm FIFO. The I2C function does

not use the FIFO.

7.23.3.2 SPI serial I/O (SPIO) controller

Features

• Maximum supported bit rate for SPI master mode (transmit/receive) is 32 Mbit/s. The

maximum supported bit rate for SPI slave receive mode is 25 Mbit/s and for SPI slave

transmit mode is 16 Mbits/s.

• Master and slave operation.

• Data frames of 4 to 16 bits supported directly. Larger frames supported by software.

• The SPI function supports separate transmit and receive FIFOs with eight entries

each.

• Supports DMA transfers: SPIn transmit and receive functions can operated with the

system DMA controller.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Up to Four Slave Select input/outputs with selectable polarity and flexible usage.

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