LPC55S69JBD64 datasheet(2/140 Pages) NXP

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LPC55S6x

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Product data sheet

Rev. 2.4 — 8 December 2022

2 of 138

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller



CASPER Crypto co-processor is provided to enable hardware acceleration for various

functions required for certain asymmetric cryptographic algorithms, such as, Elliptic

Curve Cryptography (ECC).



PowerQuad hardware accelerator for (fixed and floating point unit) CMSIS DSP

functions with support of SDK software API faster execution of ARM CMSIS instruction

set.



On-chip memory:



Up to 640 KB on-chip flash program memory with flash accelerator and 512 byte

page erase and write.



Up to 320 KB total SRAM consisting of 32 KB SRAM on Code Bus, 272 KB SRAM

on System Bus (272 KB is contiguous), and additional 16 KB USB SRAM on

System Bus which can be used by the USB interface or for general purpose use.



PRINCE module for real-time encryption of data being written to on-chip flash and

decryption of encrypted flash data during read to allow asset protection, such as

securing application code, and enabling secure flash update.



On-chip ROM bootloader supports:



Booting of images from on-chip flash



Supports CRC32 image integrity checking.



Supports flash programming through In System Programming (ISP) commands

over following interfaces: USB0/1 interfaces using HID Class device, UART

interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9)

using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)



ROM API functions: Flash programming API, Power control API, and Secure

firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).



Supports booting of images from PRINCE encrypted flash regions.



Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1

(RSA-4096).



Supports setting a sealed part to Fault Analysis mode through Debug

authentication.



Secure Boot support:



Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic

signature verification.



Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).



Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).



Uses x509 certificate format to validate image public keys.



Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys,

Root of Trust establishment by storing the SHA-256 hash digest of the hashes of

four RoT public keys in protected flash region (PFR).



Supports anti-rollback feature using image key revocation and supports up to 16

Image key certificates revocations using Serial Number field in x509 certificate.



Supports Device Identifier Composition Engine (DICE) Specification (version

Family 2.0, Level 00 Revision 69) specified by Trusted Computing Group.



Serial interfaces:



Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7

and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which

is dedicated for high-speed SPI) can be selected by software to be a USART, SPI,

I2C, and I2S interface. Each Flexcomm Interface includes a FIFO that supports

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