LPC55S69JBD64 datasheet(3/140 Pages) NXP

3 / 140 page

LPC55S6x

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Product data sheet

Rev. 2.4 — 8 December 2022

3 of 138

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

USART, SPI, and I2S. A variety of clocking options are available to each Flexcomm

Interface, including a shared fractional baud-rate generator, and time-out

feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I2S.



I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to

1Mbit/s and with multiple address recognition and monitor mode. Two sets of true

I2C pads also support high-speed Mode (3.4 Mbit/s) as a slave.



USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA

controller supporting crystal-less operation in device mode using software library

example in technical note (TN00063).



USB 2.0 high-speed host/device controller with on-chip high-speed PHY.



Digital peripherals:



DMA0 controller with 23 channels and up to 22 programmable triggers, able to

access all memories and DMA-capable peripherals.



DMA1 controller with 10 channels and up to 15 programmable triggers, able to

access all memories and DMA-capable peripherals.



Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.

SDIO with support for up to two cards. Supported card types are MMC, SDIO, and

CE-ATA. Supports SD2.0, and SDR25 (52MHz).



CRC engine block can calculate a CRC on supplied data using one of three

standard polynomials with DMA support.



Up to 64 General-Purpose Input/Output (GPIO) pins.



GPIO registers are located on the AHB for fast access. The DMA supports GPIO

ports.



Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,

falling or both input edges.



Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.



I/O pin configuration with support for up to 16 function options.



Programmable Logic Unit (PLU) to create small combinatorial and/or sequential

logic networks including state machines.



Security Features:



ARM TrustZone® enabled.



AES-256 encryption/decryption engine with keys fed directly from PUF or a

software supplied key



Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA

controller.



Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint.

PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes

hardware for key extraction.



True Random Number Generator (TRNG).



128 bit unique device serial number for identification (UUID).



Secure GPIO.



Timers:



Five 32-bit standard general purpose asynchronous timers/counters, which support

up to four capture inputs and four compare outputs, PWM mode, and external

count input. Specific timer events can be selected to generate DMA requests.

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