LPC55S69JBD64 datasheet(48/140 Pages) NXP

48 / 140 page

LPC55S6x

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Product data sheet

Rev. 2.4 — 8 December 2022

48 of 138

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.19 APB peripherals

Table 7 provides details of the addresses for APB peripherals. APB peripherals have both

secure and non-secure access possibilities.

Table 7.

APB peripherals memory map

APB

bridge

Non-secure

base address

Secure

base address

Peripheral

0x4000 0000 0x5000 0000 Syscon.

0x4000 1000 0x5000 1000 IOCON. Pin function selection and pin control setup.

0x4000 2000 0x5000 2000 Group GPIO input interrupt 0 (GINT0)

0x4000 3000 0x5000 3000 Group GPIO input interrupt 1 (GINT1)

0x4000 4000 0x5000 4000 Pin interrupt and pattern match (PINT)

0x4000 5000 0x5000 5000 Secure pin interrupt and pattern match.

0x4000 6000 0x5000 6000 Input multiplexing 0 and frequency measure.

0x4000 7000 0x5000 7000 Reserved.

0x4000 8000 0x5000 8000 CT32B0 (standard counter/timer 0).

0x4000 9000 0x5000 9000 CT32B1 (standard counter/timer 1).

0x4000 C000 0x5000 C000 WWDT0 (windowed watchdog timer 0).

0x4000 D000 0x5000 D000 MRT (Multi-Rate Timer).

0x4000 E000 0x5000 E000 Utick (micro-tick timer).

0x4001 0000 0x5001 0000 ACMP0 (analog comparator).

0x4001 3000 0x5001 3000 Analog controls.

0x4001 5000 0x5001 5000 Reserved.

0x4002 3000 0x5002 3000 Sysctl (I2S signal sharing)

0x4002 8000 0x5002 8000 CT32B2 (standard counter/timer 2).

0x4002 9000 0x5002 9000 CT32B3 (standard counter/timer 3).

0x4002 A000 0x5002 A000 CT32B4 (standard counter/timer 4).

0x4002 C000 0x5002 C000 RTC & Wake-up timer.

0x4002 D000 0x5002 D000 OS_Event Timer.

0x4003 4000 0x5003 4000 Flash controller.

0x4003 5000 0x5003 5000 PRINCE dynamic encrypt/decrypt

0x4003 8000 0x5003 8000 USB HS Phy.

0x4003 A000 0x5003 A000 True Random Number Generator.

0x4003 B000 0x5003 B000 PUF (Physical Unclonable Function).

0x4003 D000 0x5003 D000 PLU (Programmable Logic Unit).

LPC55S69JBD64 Datasheet(PDF) 48 Page - NXP Semiconductors

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