 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LPC55S69JBD64 Datasheet(PDF) 53 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
LPC55S69JBD64 Datasheet(HTML) 53 Page - NXP Semiconductors |
|
|
53 / 140 page  LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2022. All rights reserved. Product data sheet Rev. 2.4 — 8 December 2022 53 of 138 NXP Semiconductors LPC55S6x 32-bit ARM Cortex-M33 microcontroller 7.22.4 Brownout detection The LPC55S6x includes one Brown-out detector to monitor the voltage of VBAT. If the voltage falls below one of the selected voltages, the BOD asserts an interrupt to the NVIC or issues a reset. Fig 7. Clock generation (Part 2 of 2) FRGCTRL[15:0] Flexcomm clock select FCCLKSEL[2:0] pll0_clk_div fro_12m fro_hf_div main_clk Fractional Rate Divider (FRG) fro_1m CTimer clock select CTIMERCLKSEL[2:0] to CTimer main_clk 32k_osc PLL1 Settings PLL1 pll1_clk fro_1m fro_12m 011 001 010 000 111 clk_in 32k_osc “none” PLL1 clock select PLL1CLKSEL[2:0] One per Flexcomm (mclk_in only connected if I2S is present in that Flexcomm, the High Speed SPI has the same clocking, without mclk_in or FRG) to FCLK of Flexcomm[n] 011 001 010 000 100 101 110 111 "none" mclk_in fro_hf mclk_in "none" pll0_clk One per CTimer fro_1m 32k_osc Trace Clock Select TRACECLKSEL[2:0] to Trace Clock for SWO fro_1m 32k_osc "none" 111 001 010 000 TRACECLKDIV Trace Clock Divider Systick Clock Select SYSTICKCLKSEL[2:0] to System Tick Timer fro_1m 32k_osc "none" 111 001 010 000 SYSTICKCLKDIV Systick Clock Divider One per CPU main_clk 180814 SDIO clock select SDIOCLKSEL[2:0] SDIOCLKDIV SDIO Clock Divider to SDIO function clock fro_hf main_clk 101 001 011 000 111 pll0_clk pll1_clk “none” CLKOUT select CLKOUTSEL[2:0] CLKOUTDIV CLKOUT Divider pll1_clk 32k_osc fro_1m fro_hf main_clk pll0_clk "none" 011 001 010 000 100 101 110 111 CLKOUT clk_in SCT clock select SCTCLKSEL[2:0] SCTCLKDIV SCTimer/PWM Clock Divider to SCTimer/PWM input clock 7 011 001 010 000 101 111 clk_in main_clk pll0_clk fro_hf mclk_in “none” main_clk 100 001 011 000 101 110 111 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
