EM78P813

8-bit OTP Micro-controller

__________________________________________________________________________________________________________________________________________________________________

* This specification is subject to change without notice.

28

2004/8/19

(V1.6)

Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen!

The status after wake-up and the wake-up sources list as the table below.

Wakeup signal

SLEEP mode

GREEN mode

NORMAL mode

RA(7,6)=(0,0)

+ SLEP

RA(7,6)=(x,0)

no SLEP

RA(7,6)=(x,1)

no SLEP

TCC time out

IOCF bit 0=1

And "ENI"

No function

Interrupt

(jump to address 8

at page0)

Interrupt

(jump to address

8 at page0)

COUNTER1 time out

IOCF bit 1=1

And "ENI"

No function

Interrupt

(jump to address 8

at page0)

Interrupt

(jump to address

8 at page0)

COUNTER2 time out

IOCF bit 2=1

And "ENI"

No function

Interrupt

(jump to address 8

at page0)

Interrupt

(jump to address

8 at page0)

WDT time out

RESET and

Jump to address

0

RESET and Jump

to address 0

RESET and

Jump to address

0

PORT7

Any one bit in IOCE

page0 = 1

And "ENI"

RESET and

Jump to address

0

Interrupt

(jump to address 8

at page0)

Interrupt

(jump to address

8 at page0)

DED interrupt

IOCE page1 bit 6 = 1

And RF bit3 logic level

variation

(switch by EDGE bit)

And “ENI”

No function

Interrupt

(jump to address 8

at page0)

Interrupt

(jump to address

8 at page0)

Stack overflow

IOC5 page1 bit7=1

& RF bit 4: 0

1

And “ENI”

No function

Interrupt

(jump to address 8

at page0)

Interrupt

(jump to address

8 at page0)

<Note> Stack overflow interrupt function is exist in ROM less and OTP chip only.

<Note> PORT70 ~ PORT76 's wakeup function is controlled by IOCE PAGE0 bit 0~bit 6 and ENI instruction. They

are falling edge trigger.

PORT77 's wakeup function is controlled by IOCE PAGE0 bit 7 . It can be trigger in falling edge or rising

edge (controlled by CONT register).

PAGE1 LCD address

7

6

5

4

3

2

1

0

LCDA7

LCDA6

LCDA5

LCDA4

LCDA3

LCDA2

LCDA1

LCDA0

Bit 0 ~ Bit 7 (LCDA0 ~ LCDA7) : LCD address for internal LCD RAM reading or writing

The data in the internal LCD RAM correspond to the COMMON and SEGMENT signals as the table .

COM31 ~ COM24

(set R9 PAGE1

bit7=1)

COM23 ~ COM16

(set R9 PAGE1

bit7=1)

COM15 ~COM8

(set R9 PAGE1

bit7=0)

COM7 ~ COM0

(set R9 PAGE1

bit7=0)

Address 180H

Address 100H

Address 080H

Address 000H

SEG0

Address 181H

Address 101H

Address 081H

Address 001H

SEG1

Address 182H

Address 102H

Address 082H

Address 002H

SEG2

:

:

:

:

:

:

:

:

:

: