FXPS7115D4S datasheet(32/74 Pages) NXP

32 / 74 page

NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit

Symbol

Description

COMM_ERR

The communication error flag is set if any bit in DEVSTAT3 is set:

COMM_ERR = MISO_ERR

MEMTEMP_ERR

The memory error flag is set if any bit in DEVSTAT2 is set:

MEMTEMP_ERR = F_OTP_ERR | U_OTP_ERR | U_RW_ERR | U_W_ACTIVE |

TEMP0_ERR

3[1]

SUPPLY_ERR

The supply error flag is set if any bit in DEVSTAT1 is set:

SUPPLY_ERR = VCCUV_ERR | INTREG_ERR | INTREGA_ERR | INTREGF_ERR |

CONT_ERR

TESTMODE

The test mode bit is set if the device is in test mode. The TESTMODE bit can be cleared by

a test mode operation or by a power cycle.

0 — Test mode is not active

1 — Test mode is active

DEVRES

The device reset bit is set following a device reset. This error is cleared by a read of the

DEVSTAT register through any communication interface or on a data transmission that

includes the error in the status field.[2]

0 — Normal operation

1 — Device reset occurred

DEVINIT

The device initialization bit is set following a device reset. The bit is cleared once sensor data

is valid for read through one of the device communication interfaces (tPOR_DataValid).

0 — Normal operation

1 — Device initialization in process

Table 38. DEVSTAT - device status register (address 01h) bit description...continued

[1]

See Section 7.7.4 bit 3, supply error reporting disable bit (SUP_ERR_DIS).

[2]

After POR and/or soft reset, see Section 7.5.5 for initialization sequence.

7.7.2.2 DEVSTAT1 - device status register (address 02h)

Bit[1][2]

Symbol

VCCUV_

ERR

reserved

INTREGA_

ERR

INTREG_

ERR

INTREGF_

ERR

CONT_ERR

Reset

Access

Table 39. DEVSTAT1 - device status register (address 02h) bit allocation

[1]

During POR and soft reset ignore DEVSTAT1 error flags, refer to Section 7.5.5.

[2]

A common timer is used for all error bits in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV. This bit is cleared based

on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 7.7.4.

Bit[1][2] Symbol

Description

VCCUV_ERR

The VCC undervoltage error bit is set if the VCC voltage falls below the voltage specified in

Table 104. See Section 7.1 for details on the VCC undervoltage monitor.

0 — No error detected

1 — VCC voltage low

Table 40. DEVSTAT1 - device status register (address 02h) bit description

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

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