FXPS7115D4S datasheet(57/74 Pages) NXP

57 / 74 page

NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

11 Dynamic characteristics

VCC_min ≤ (VCC – VSS) ≤ VCC_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified.

Symbol

Parameter

Condition

Min

Typ

Max

Units

I2C

tSCL_100

tSCLK_400

tSCLK_1000

Clock (SCL) period

(30 % of VCC to 30 % of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

9.50

2.37

1.00

—

μs

tSCLH_100

tSCLH_400

tSCLH_1000

Clock (SCL) high time

(70 % of VCC to 70 % of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode (not

compliant with UM10204,

rev.6)

[1]

—

4.00

0.60

0.50

—

μs

tSCLL_100

tSCLL_400

tSCLL_1000

Clock (SCL) low time

(30 % of VCC to 30 % of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

4.70

1.30

0.50

—

μs

tSRISE_100

tSRISE_400

tSRISE_1000

Clock (SCL) and data (SDA) risetime

(30 % of VCC to 70 % of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

1000

300

120

tSFALL_100

tSFALL_400

tSFALL_1000

Clock (SCL) and data (SDA) fall time

(70 % of VCC to 30 % of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

300

120

tSETUP_100

tSETUP_400

tSETUP_1000

Data input setup time

(SDA = 30/70 % of VCC to SCL = 30 %

of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

250

100

—

tHOLD_100

tHOLD_400

tHOLD_1000

Data input hold time

(SCL = 70 % of VCC to SDA = 30/70 %

of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

900

300

tSTARTSETUP_100

tSTARTSETUP_400

tSTARTSETUP_1000

Start condition setup time

(SDA = 30/70 % of VCC to SCL = 30 %

of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

4.70

0.60

0.26

—

μs

tSTARTHOLD_100

tSTARTHOLD_400

tSTARTHOLD_1000

Start condition hold time

(SCL = 70 % of VCC to SDA = 30/70 %

of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

4.00

0.60

0.26

—

μs

tSTOPSETUP_100

tSTOPSETUP_400

tSTOPSETUP_1000

Stop condition setup time

(SDA = 30/70 % of VCC to SCL = 30 %

of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

4.00

0.60

0.26

—

μs

tVALID_100

tVALID_400

tVALID_1000

SCLK low to data valid

(SCL = 30 % of VCC to SDA = 30/70 %

of VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

3.45

0.90

0.45

μs

tFREE_100

tFREE_400

tFREE_1000

Bus free time

(SDA = 70 % of VCC to SDA = 70 % of

VCC)

100 kHz mode

400 kHz mode

1000 kHz mode

[1]

—

4.00

1.30

0.50

—

μs

CBUS

Bus capacitive load

[2] —

—

400

SPI

tSCLK

Serial interface timing[3]

Clock (SCLK) period (10 %

of VCC to 10 % of VCC)

[1] —

—

tSCLKH

Clock (SCLK) period (90 %

of VCC to 90 % of VCC)

[1] —

—

tSCLKL

Serial interface timing[3]

Clock (SCLK) period (10 %

of VCC to 10 % of VCC)

[1] —

—

tSCLKR

Clock (SCLK) period (10 %

of VCC to 90 % of VCC)

[1] —

tSCLKF

Serial interface timing[3]

Clock (SCLK) period (90 %

of VCC to 10 % of VCC)

[1] —

Table 105. Dynamic characteristics

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

57 / 74

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