FXPS7115D4S datasheet(41/74 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

Bit

Symbol

WHO_AM_I[7:0]

Factory default (stored value)

Factory default (read value)

Access

R/W

Table 61. WHO_AM_I - device identification register (address 3Eh) bit allocation

The default register value is 00h. If the register value is 00h, a value of C4h is transmitted

in response to a read command. For all other register values, the actual register value is

transmitted in response to a read command.

WHO_AM_I register value (hex)

Response to a register read command

00h

C4h

01h to FFh

Actual register value

Table 62. WHO_AM_I register values

7.7.10 I2C_ADDRESS - I2C client address register (address 3Fh)

The I2C client address register is a user programmed read/write register that contains the

unique I2C client address. The register is readable in all modes. This register is included

in the read/write array error detection.

Bit

Symbol

I2C_ADDRESS[7:0]

Factory Default (stored value)

Factory Default (read value)

Access

R/W

Table 63. I2C_ADDRESS - I2C client address register (address 3Fh) bit allocation

The default register value is 00h. If the register value is 00h, the I2C client address is

60h and a value of 60h is transmitted in response to a read command. If the register is

written to a value other than 00h, the I2C client address is the lower seven bits of the

actual register value and the actual register value is transmitted in response to a read

command.

7.7.11 DSP Configuration Registers (DSP_CFG_Ux)

The DSP Configuration registers (DSP_CFG_Ux) are a series of registers that affect the

DSP data path.

There are 4 DSP Configuration registers which are DSP_CFG_U1, DSP_CFG_U3,

DSP_CFG_U4, and DSP_CFG_U5.

7.7.11.1 Self-test control bits

The self-test control bits of the DSP user configuration register (DSP_CFG_U5, address

44h) select one of the various analog and digital self-test features of the device as

shown in Table 73. The self-test control bits are not included in the read/write array error

detection.

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

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