FXPS7115D4S datasheet(72/74 Pages) NXP

72 / 74 page

NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

Tab. 71. DSP_CFG_U5 - DSP user configuration #5

Tab. 72. DSP_CFG_U5 - DSP user configuration #5

Tab. 73. Self-test control bits (ST_CTRL[3:0]) ...............44

Tab. 74. INT_CFG - interrupt configuration register

(address 45h) bit allocation .............................44

Tab. 75. INT_CFG - interrupt configuration register

(address 45h) bit description ...........................45

Tab. 76. P_INT_HI, P_INT_LO - interrupt window

comparator threshold registers (address

46h to 49h) bit allocation .................................45

Tab. 77. P_CAL_ZERO - pressure calibration

registers (address 4Ch, 4Dh) bit allocation ......46

Tab. 78. DSP_STAT - DSP-specific status register

(address 60h) bit allocation .............................46

Tab. 79. DSP_STAT - DSP-specific status register

(address 60h) bit description ...........................46

Tab. 80. DEVSTAT_COPY - device status copy

Tab. 81. SNSDATA0_L, SNSDATA0_H - sensor

data #0 registers (addresses 62h, 63h) bit

allocation ......................................................... 47

Tab. 82. SNSDATA1_L, SNSDATA1_H - sensor

data #1 registers (address 64h, 65h) bit

allocation ......................................................... 48

Tab. 83. SNSDATA0_TIMEx - timestamp register

(address 66h to 6Bh) bit allocation ..................48

Tab. 84. P_Max and P_Min registers (address 6Ch

to 6Fh) bit allocation ....................................... 49

Tab. 85. FRT - free running timer registers

(addresses 78h to 7Dh) bit allocation ..............49

Tab. 86. IC TYPE REGISTER (ICTYPEID address

C0h) bit allocation ........................................... 49

Tab. 87. IC MANUFACTURER REVISION

allocation ......................................................... 50

Tab. 88. IC MANUFACTURER IDENTIFICATION

allocation ......................................................... 50

Tab. 89. PN0 Register (address C4h) bit allocation .......50

Tab. 90. PN1 Register (address C5h) bit allocation .......50

Tab. 91. SN0 Register (address C6h) bit allocation .......51

Tab. 92. SN1 Register (address C7h) bit allocation .......51

Tab. 93. SN2 Register (address C8h) bit allocation .......51

Tab. 94. SN3 Register (address C9h) bit allocation .......51

Tab. 95. SN4 Register (address CAh) bit allocation ...... 51

Tab. 96. ASICWFR# Register (address CBh) bit

allocation ......................................................... 51

Tab. 97. ASICWFR_X Register (address CCh) bit

allocation ......................................................... 52

Tab. 98. ASICWFR_Y Register (address CDh) bit

allocation ......................................................... 52

Tab. 99. ASICWLOT_L Register (address D0h) bit

allocation ......................................................... 52

Tab. 100. ASICWLOT_H Register (address D1h) bit

allocation ......................................................... 52

Tab. 101. Lock and CRC Register bit definitions .............53

Tab. 102. Maximum ratings .............................................54

Tab. 103. Electrical characteristics — supply and I/O ..... 55

Tab. 104. Static characteristics ....................................... 55

Tab. 105. Dynamic characteristics .................................. 57

Tab. 106. External component recommendations for

I2C ...................................................................61

Tab. 107. External component recommendations for

SPI ...................................................................61

Tab. 108. Revision history ...............................................68

Figures

Fig. 1.

Block diagram of FXPS7115D4S ...................... 3

Fig. 2.

Pin configuration for 16-pin HQFN .................... 3

Fig. 3.

Voltage regulation and monitoring .....................5

Fig. 4.

User-controlled PABS common mode self-

test flowchart .....................................................6

Fig. 5.

ΣΔ converter block diagram .............................. 7

Fig. 6.

Signal chain diagram ........................................ 8

Fig. 7.

Sinc filter response ........................................... 8

Fig. 8.

800 Hz, 4-pole, low-pass filter response ........... 9

Fig. 9.

800 Hz, 4-pole output signal delay ..................10

Fig. 10.

1000 Hz, 4-pole, low-pass filter response ....... 10

Fig. 11.

1000 Hz, 4-pole output signal delay ................11

Fig. 12.

Temperature sensor signal chain block

diagram ............................................................12

Fig. 13.

Common mode error detection signal chain

block diagram ..................................................12

Fig. 14.

I2C bit transmissions .......................................13

Fig. 15.

I2C start condition ........................................... 13

Fig. 16.

I2C byte transmissions ....................................14

Fig. 17.

I2C acknowledge and not acknowledge

transmission .................................................... 14

Fig. 18.

I2C stop condition ........................................... 15

Fig. 19.

I2C timing diagram ..........................................17

Fig. 20.

Standard 32 Bit SPI protocol timing

diagram ............................................................18

Fig. 21.

SPI data output verification ............................. 27

Fig. 22.

SPI timing diagram ..........................................27

Fig. 23.

Absolute pressure accuracy as a function

of temperature .................................................60

Fig. 24.

Absolute pressure accuracy multiplier over

life ....................................................................60

Fig. 25.

I2C application diagram of FXPS7115D4S ......61

Fig. 26.

SPI application diagram for FXPS7115D4S .... 61

Fig. 27.

Package outline HQFN (SOT1573-1) ..............62

Fig. 28.

Package outline detail HQFN (SOT1573-1) .... 63

Fig. 29.

Package outline note HQFN (SOT1573-1) ......64

Fig. 30.

SOT1573-1 PCB design guidelines - Solder

mask opening pattern ......................................65

Fig. 31.

SOT1573-1 PCB design guidelines - I/O

pads and solderable area ............................... 66

Fig. 32.

SOT1573-1 PCB design guidelines - Solder

paste stencil .................................................... 67

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

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