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FXPS7115D4S Datasheet(PDF) 71 Page - NXP Semiconductors |
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FXPS7115D4S Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 74 page  NXP Semiconductors FXPS7115D4S Digital absolute pressure sensor, 40 kPa to 115 kPa Tables Tab. 1. Ordering information ..........................................2 Tab. 2. Ordering options ................................................2 Tab. 3. Pin description ...................................................4 Tab. 4. Self-test control register .................................... 7 Tab. 5. Self-test control bits for sense data fixed value verification ............................................... 7 Tab. 6. IIR low pass filter coefficients ............................9 Tab. 7. Scaling parameters ......................................... 11 Tab. 8. Temperature conversion variables .................. 12 Tab. 9. Sensor data register read wrap-around description ....................................................... 16 Tab. 10. SPI command format ...................................... 18 Tab. 11. SPI command summary ..................................19 Tab. 12. SPI response format ....................................... 19 Tab. 13. Register read command message format ....... 20 Tab. 14. Register read command message bit field descriptions ..................................................... 20 Tab. 15. Register read response message format ........ 20 Tab. 16. Register read response message bit field descriptions ..................................................... 21 Tab. 17. Register write command message format ....... 21 Tab. 18. Register write command message bit field descriptions ..................................................... 21 Tab. 19. Register write response message format ........ 22 Tab. 20. Register write response message bit field descriptions ..................................................... 22 Tab. 21. Sensor data request command message format .............................................................. 22 Tab. 22. Sensor data request command message bit field descriptions ........................................ 22 Tab. 23. Sensor data request response message format – 12 bit data length ..............................23 Tab. 24. Sensor data request response message bit field descriptions ............................................. 23 Tab. 25. Reserved command message format ..............23 Tab. 26. Reserved command message bit field descriptions ..................................................... 23 Tab. 27. Reserved command response message format .............................................................. 24 Tab. 28. Reserved command response message bit field descriptions ............................................. 24 Tab. 29. SPI Command Message CRC ........................ 24 Tab. 30. SPI Response Message CRC .........................25 Tab. 31. Expected initial responses after tPOR_ DataValid post POR ........................................ 25 Tab. 32. Expected initial responses after tPOR_ DataValid post soft reset ................................. 25 Tab. 33. Basic status field for responses to register commands .......................................................26 Tab. 34. Detailed status bit field descriptions ................26 Tab. 35. User-accessible data — sensor specific information .......................................................28 Tab. 36. COUNT - rolling counter register (address 00h) bit allocation ............................................31 Tab. 37. DEVSTAT - device status register (address 01h) bit allocation ............................................31 Tab. 38. DEVSTAT - device status register (address 01h) bit description ..........................................31 Tab. 39. DEVSTAT1 - device status register (address 02h) bit allocation .............................32 Tab. 40. DEVSTAT1 - device status register (address 02h) bit description ...........................32 Tab. 41. DEVSTAT2 - device status register (address 03h) bit allocation .............................33 Tab. 42. DEVSTAT2 - device status register (address 03h) bit description ...........................33 Tab. 43. DEVSTAT3 - device status register (address 04h) bit allocation .............................34 Tab. 44. DEVSTAT3 - device status register (address 04h) bit description ...........................34 Tab. 45. TEMPERATURE - temperature register (address 0Eh) bit allocation .............................35 Tab. 46. DEVLOCK_WR - lock register writes register (address 10h) bit allocation ................ 35 Tab. 47. DEVLOCK_WR - lock register writes register (address 10h) bit description .............. 35 Tab. 48. Device reset command sequence ...................36 Tab. 49. WRITE_OTP_EN – write OTP enable register – (address 11h) bit allocation ............. 36 Tab. 50. Writes for OTP registers ................................. 36 Tab. 51. UF_REGION_W - UF region selection register (address 14h) bit allocation ................ 37 Tab. 52. UF_REGION_R - UF region selection register (address 15h) bit allocation ................ 38 Tab. 53. REGION_LOAD Bit Definitions ....................... 38 Tab. 54. REGION_ACTIVE Bit Definitions .................... 38 Tab. 55. SOURCEID_0 - source identification register (address 1Ah) bit allocation ................39 Tab. 56. SOURCEID_1 - source identification register (address 1Bh) bit allocation ................39 Tab. 57. Source ID enable ............................................ 39 Tab. 58. SPI_CFG Register (address 3Dh) bit allocation ......................................................... 40 Tab. 59. DATASIZE Bit Definition ..................................40 Tab. 60. SPI CRC Definition ......................................... 40 Tab. 61. WHO_AM_I - device identification register (address 3Eh) bit allocation .............................41 Tab. 62. WHO_AM_I register values .............................41 Tab. 63. I2C_ADDRESS - I2C client address register (address 3Fh) bit allocation ................41 Tab. 64. DSP_CFG_U1 - DSP user configuration #1 register (address 40h) bit allocation ................ 42 Tab. 65. Low-pass filter selection bits (LPF[3:0]) ...........42 Tab. 66. DSP_CFG_U3 - DSP user configuration #3 register (address 42h) bit allocation ................ 42 Tab. 67. DATATYPE0[1:0] ............................................. 43 Tab. 68. DATATYPE1[1:0] ............................................. 43 Tab. 69. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit allocation ................ 43 Tab. 70. DSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit description .............. 43 FXPS7115D4S All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Objective data sheet Rev. 1 — 9 August 2022 71 / 74 |
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