EM6821 datasheet(43/68 Pages) EMMICRO

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EM6821

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11. Supply Voltage Level Detector

The EM6821 has a built-in Supply Voltage Level Detector (SVLD) circuitry, such that the CPU can compare the

supply voltage against a pre-selected value. During sleep mode this function is inhibited.

The CPU activates the supply voltage level

detector by writing VldStart = 1 in the register

RegVldCntl. The actual measurement starts on

the next Ck[9] rising edge and lasts during the

Ck[9] high period (2 ms at 32 KHz). The busy

flag VldBusy stays high from VldStart set until

the measurement is finished. The worst case

time until the result is available is 1.5 Ck[9]

prescaler clock periods (32 KHz -> 6 ms). The

detection level must be defined in register

RegVldLevel before the VldStart bit is set.

During the actual measurement (2 ms) the

device will draw an additional 5 µA of IVDD

current. After the end of the measure the result

is available by inspection of the bit VldResult.

If the result is read 0, then the power supply

voltage was greater than the detection level value. If read 1, the power supply voltage was lower than the

detection level value. During each read while Busy=1 the VldResult is not guaranteed.

11.1 SVLD Register

Table 11.1.1 Register RegVldCntl

Bit

Name

Reset

R/W

Description

VldResult

Vld result flag

VldStart

Vld start

VldBusy

Vld busy flag

NoOscWD

R/W

No Oscillator watchdog

NoLogicWD

R/W

No logic watchdog

R*; Read value while VLDBusy=1 is not guaranteed.

Table 11.1.2 Register RegVldLevel (Detection Level Value)

Bit

Name

Reset

R/W

Description

not active

VldLevel2

R/W

Vld level selection

VldLevel1

R/W

Vld level selection

VldLevel0

R/W

Vld level selection

Table 11.1.3 Voltage Level Detector Value Selecting

VldLevel2

VldLevel1

VldLevel0

Typical voltage level

Level1

4.0

Level2

3.0

Level3

2.4

Level4

2.0

Level5

1.75

Level6

1.5

Level7

1.35

Level8

1,20

Figure 32. SVLD Timing Diagram

VBAT =VDD

Compare Level

Ck[9] (256 Hz)

CPU starts

measure

Busy Flag

Measure

Result

Read Result

SVLD > VBAT

SVLD < VBAT

CPU starts

measure

EM6821 Datasheet(PDF) 43 Page - EM Microelectronic - MARIN SA

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