NORAB100 datasheet(16/46 Pages) ETC

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NORA-B1 series - Data sheet

UBX-20027119 - R10

Interfaces

Page 16 of 46

C1 – Public

☞ Most input/output pins on the module are shared between the digital interfaces, analog

interfaces, and GPIOs. Unless otherwise stated, all functions can be assigned to any pin that is not

already occupied.

☞ Four of the SPI interfaces share common hardware with I2C interfaces and cannot be used

simultaneously. If both I2C interfaces are in use only one SPI interface is available.

2.5.1 Universal Asynchronous Receiver/Transmitter (UART)

The 4-wire UART interface supports hardware flow control with baud rates up to 1 Mbps. Up to four

instances can be defined on the application core, and one on the network core.

Other characteristics of the UART interface include:

•

Pin configuration:

TXD, data output pin

RXD, data input pin

RTS, Request To Send, flow control output pin (optional)

CTS, Clear To Send, flow control input pin (optional)

•

Hardware flow control or no flow control is supported.

•

Power saving indication available on the hardware flow control output (RTS pin): The line is driven

to the OFF state when the module is not ready to accept data signals.

•

Programmable baud rate generator allows most industry standard rates, as well as non-standard

rates up to 1 Mbps.

•

Frame format configuration:

8 data bits

Even or no-parity bit

1 stop bit

•

8N1default frame configuration, meaning eight (8) data bits, no (N) parity bit, and one (1) stop bit.

•

Frames are transmitted in such a way that the least significant bit (LSB) is transmitted first.

2.5.2 Serial Peripheral Interface (SPI)

NORA-B1 supports up to four Serial Peripheral Interfaces with serial clock frequencies of up to

32 MHz.

Other characteristics of the SPI interfaces include:

•

Pin configuration in master mode:

SCLK, Serial clock output, up to 32 MHz

MOSI, master output to slave input data line

MISO, master input from slave output data line

CS, Chip select output, active low, selects which peripheral on the bus to talk to.

Only one select line is enabled by default but more can be added by customizing a GPIO pin.

DCX, Data/Command signal. An optional signal used by SPI slaves to distinguish between

SPI commands and data

•

Pin configuration in peripheral mode:

SCLK, Serial clock input

MOSI, master output to slave input data line

MISO, master input from slave output data line

CS, Chip select input, active low, connects/disconnects the lave interface from the bus.

•

Both master and slave modes are supported on all interfaces.

•

The serial clock supports both normal and inverted clock polarity (CPOL) and data should be

captured on rising or falling clock edge (CPHA).

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