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89TSF552 Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # 89TSF552
Description  Switch Fabric Data Sheet
PDF  39 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

89TSF552 Datasheet(HTML) 3 Page - Renesas Technology Corp

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June 17, 2005
IDT 89TSF552
*Notice: The information in this document is subject to change without notice
Signal Name
I/O Type
Dir.
Freq.
Remarks
SD[2:0]_REFCLKN
(pins A25, Y39, AW26)
Serdes diff clock
I
250MHz
Reference clocks for both Rx and Tx.
The reference clock (SD[n]_REFCLKN and
SD[n]_REFCLKP) must be synchronous to twice the sys-
tem clock (SYS_CLK) input.
If an entire SerDes group is not used, the reference clock
pins for that group should be pulled down to VSS using a
300
Ω to 1kΩ resistor.
SD[2:0]_REFCLKP
(pins A26, AA39, AW25)
Serdes diff clock
I
250MHz
SD[2:0]_REF_RES
(pins D26, AA36, AT25)
Serdes Bidi
O
—
Reference resistor pins used to generate bias currents for
both Rx and Tx.
To ensure proper biasing, connect each of these to VSS
through a 3.09 k
Ω 1% resistor.
If an entire SerDes group is not used, the reference resistor
pins for that group should be connected to VDD_SD (1.8V).
VDD_SD[2:0]_PLL
(pins J23, Y31, AL24)
VAA18
P
—
SerDes common VDD = 1.8V. These are PLL analog
power inputs and should be well filtered.
VSS_SD[2:0]_PLL
(pins K22, W31, AL23)
VSS
P
—
SerDes PLL ground
VDD_REFCLK[2:0]
(pins J24, AA31, AK22)
VAA33
P
—
SerDes common VDD = 3.3V
RXN[23:0]
Serdes diff input
I
—
SerDes Rx differential pairs.
A link should be left open (n.c.) if it is not used
RXP[23:0]
Serdes diff input
I
—
TXN[23:0]
Serdes diff output
O
—
SerDes Tx differential pairs.
A link should be left open (n.c.) if it is not used
TXP[23:0]
Serdes diff output
O—
VDD_SD
VAA18
P
—
SerDes VDD (1.8V)
VDD_TX
VAA25
P
—
SerDes VDD (2.5V)
VSS
VSS
P
—
Serdes ground included in Table 8 (89TSF552 Misc.
Pins)
Table 2 89TSF552 SerDes Pins
Signal Name
Type
Dir.
Freq.
Remarks
ZBUS_AVALID_N (pin AR11)3.3V LVTTL
I
33MHz
33K
Ω internal pullup
ZBUS_CLK (pin AW7)
3.3V LVTTL
I
33MHz
N/A
ZBUS_AD[15:0]
3.3V LVTTL
B
33MHz
33K
Ω internal pullup
ZBUS_DEVID[4:0]
3.3V LVTTL
I
—
33K
Ω internal pullup
ZBUS_DVALID_N (pin AV10)
3.3V LVTTL
B
33MHz
33K
Ω internal pullup
ZBUS_INT_N[2:0]
(pins AW11, AV11, AU11)
3.3V LVTTL
O
—
33K
Ω internal pullup
ZBUS_PRTY (pin AV9)
3.3V LVTTL
B
33MHz
33K
Ω internal pullup
Table 3 89TSF552 ZBus Pins



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