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June 17, 2005

IDT 89TSF552

*Notice: The information in this document is subject to change without notice

89TSF552 Electrical and Timing Characteristics

Some data are TBD and will be published as they become available.

The specifications are subject to change without notice.

89TSF552 Absolute Maximum Ratings

The absolute maximum ratings are the maximum conditions that the device can withstand without sustaining permanent damage. Exceeding any

of these conditions could result in permanent damage to the device. Normal operation should not be expected at these conditions. In addition, expo-

sure to absolute maximum rated conditions (or near absolute maximum rated conditions) for extended periods may affect device reliability.

Operation of the device is not guaranteed at the absolute maximum ratings, but rather at the operating conditions outlined in “89TSF552 DC Char-

acteristics” on page 8 and “89TSF552 AC Characteristics” on page 9.

Signal Name

I/O Type Dir.

Freq.

Remarks

RESET_N (pin AR12)

3.3V LVTTL

I

—

Resets the entire chip. Must be asserted for at least 16

125MHz clock cycles after the PLL power-up initialization

sequence is complete. Both assertion and deassertion are

asynchronous to all clocks.

CHN_DET_MODE (pin

AP21)

3.3V LVTTL

I

—

Channel determination method 2 enable:

0

→ system of mixed family devices, ZSF200 and 89TSF5xx.

1

→ system has only 89TSF5xx devices.

SD8_MODE (pin AR22)

3.3V LVTTL

I

—

SerDes 8-link mode:

0

→ 24 SerDes links are enabled

1

→ 8 SerDes links are enabled (links 8 through 15 are

active)

TURBO_CLK (pin AW13)

3.3V LVTTL

I

87.5MHz

Turbo interface

TURBO_SOF (pin AV13)

3.3V LVTTL

I

TURBO_DAT[2:0]

(pins AU13, AV13, AT13)

3.3V LVTTL

I

VDD

VDD18

P

—

Core VDD, 1.8V

VDD_IO

VDD33

P

—

I/O VDD, 3.3V

VDDP33

VDDP33

P

—

VDDP for LVDS input buffers, 3.3V

VDD25

VDD25

P

—

VDDO for LVDS outputs, 2.5V

VDD12

VDD12

P

—

VREF for LVDS outputs, 1.25V

VSS

VSS

P

—

Ground

Table 8 89TSF552 Misc. Pins