89TSF552 datasheet(9/39 Pages) RENESAS

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June 17, 2005

IDT 89TSF552

*Notice: The information in this document is subject to change without notice

89TSF552 AC Characteristics

Unless otherwise stated, the following parameters are provided given the conditions outlined in Table 10.

VIL33

Input low voltage for 3.3V I/O

–0.3

—

0.8

VIH33

Input high voltage for 3.3V I/O

2.0

—

VDDLVTTL33+0.5

VOL33

Output low voltage for 3.3V I/O

—

0.5

I = 12 mA for 12 mA

drivers and 16 mA for

16 mA drivers

VOH33

Output high voltage for 3.3V I/O

2.4

—

I = 12 mA for 12 mA

drivers and 16 mA for

16 mA drivers

1. 1.25V LVDS reference should be capable of sourcing and sinking this current.

Symbol

Parameter

Min

Typical Max

Units

Conditions

Input voltage range, VIA or VIB

—

2400

|VGPD| < 925 mV 1

1. VGPD is the ground potential difference between the transmitter and the receiver

VIDTH

Input differential threshold

–100

—

+100

|VGPD| < 925 mV

VHYST

Input differential hysteresis

—

RIN

Receiver differential input impedance

120

Ω

VOH

Output voltage high, VOA or VOB

—

1475

RLOAD = 100 Ω ±1%

VOL

Output voltage low, VOA or VOB

925

—

RLOAD = 100 Ω ±1%

|VOD|

Output differential voltage

250

—

400

RLOAD = 100 Ω ±1%

VOS

Output offset voltage

1125

—

1275

RLOAD = 100 Ω ±1%

|DVOD|

Change in |VOD| between ‘0’ and ‘1’

—

RLOAD = 100 Ω ±1%

DVOS

Change in VOS between ‘0’ and ‘1’

—

RLOAD = 100 Ω ±1%

ISA, ISB

Output current

—

Driver shorted to ground

ISAB

Output current

—

Drivers shorted together

Table 12 89TSF552 LVDS DC Parameters

Symbol

Parameter

Min

Typical Max

Units

fSYS

System clock frequency (125 MHz ±0.1 MHz)

124.9

125

125.1

MHz

TJSYS

Jitter requirements (peak to peak) for system clock. Peak to peak jitter require-

ments apply to entire range of allowed system clock frequencies.

—

100

DSYS

Percentage duty cycle for system clock

TRSYSCI

System clock input rise time (10% to 90%)

—

TBD

TFSYSCI

System clock input fall time (90% to 10%)

—

TBD

Table 13 89TSF552 System Clock Timing

Symbol

Parameter

Min

Typical

Max

Units

Conditions

Table 11 89TSF552 DC Characteristics (except LVDS) (Part 2 of 2)

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