DA9053 datasheet(61/185 Pages) RENESAS

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DA9053

Flexible High-Power System PMIC with 1.8 A

Switching USB Power Manager

Datasheet

Revision 2.1

31-Aug-2016

CFR0011-120-00

61 of 183

9.9

General Purpose Feedback Signal 1 (GP_FB1: EXT_WAKEUP/READY)

The feedback GP_FB1 supports two different modes. If configured as EXT_WAKEUP it is an active

high output signal to the host processor that indicates a valid wake-up event during POWER-DOWN

mode. External signals that are causing wake-up events are debounced before DA9053 assert the

EXT_WAKEUP signal. EXT_WAKEUP is released when entering the ACTIVE mode. If configured as

READY signal it indicates ongoing DVC or power sequencer activities. The signal is active low and is

asserted from DA9053 as long as the power sequencer processes IDs or DVC voltage transitions are

ongoing.

9.10 Power Domain Status (SYS_UP, PWR_UP/GP_FB2)

The power domain status indicators are active high and assigned after the sequencer has processed

all IDs of a power domain (all assigned supplies are up). When domains are disabled during power

mode transitions the status indicator is released before the DA9053 sequencer processes the last

step of a domain.

PWR_UP is one mode of the general purpose indicator GP_FB2 that can also be used as a

configurable feedback signal that is level/time controlled from the power sequencer.

9.11 Supply Rail Fault (nVDD_FAULT)

nVDD_FAULT is an active low output signal to the host processor to indicate a VDDOUT low status.

The assertion of nVDD_FAULT indicates that the main battery and the supply input voltage is low

and therefore informs the host processor that the power will shut down very soon. After that the

processor may operate for a limited time from the backup battery, which can provide power to the

processor for a few cycles. In the event of nVDD_FAULT assertion the processor may be

programmed to enter an emergency mode, for example external memory data refresh is no longer

performed.

9.12 Interrupt Request (nIRQ)

The nIRQ is an active low output signal which indicates that an interrupt causing event has occurred

and that the event and status information is available in the related registers. Such information can

be temperature and voltage of the PMIC, fault conditions, charging status, status changes at GPI

ports, and others. The event registers hold information about the events that have occurred. Events

are triggered by a status change at the monitored signals. When an event bit is set the nIRQ signal is

asserted (unless this interrupt is masked by a bit in the IRQ mask register). The nIRQ will not be

released until the event registers have been cleared.

9.13 Real Time Clock Output (OUT_32K)

The OUT_32K is an output signal that generates a buffered signal of the DA9053 32 kHz oscillator.

The 32 kHz oscillator will always run on the DA9053 following the initial start-up from NO-POWER

mode until the device has reached NO-POWER mode again. The signal output buffer can be

disabled during POWER-DOWN mode.

9.14 IO Supply Voltage (VDD_IO1 and VDD_IO2)

VDD_IO1 and VDD_IO2 are two independent IO supply rail inputs of DA9053 that can be individually

assigned to the power manager interface, power manager IOs and GPIOs. The rail assignment

determines the IO voltage levels and logical thresholds. The selection of the supply rail for GPIOs is

also partially used for their alternate functions. GPOs configured in open drain mode have to use the

VDD_IO1 rail if an internal pull-up resistor is required.

DA9053 Datasheet(PDF) 61 Page - Renesas Technology Corp

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