DA9211 datasheet(39/75 Pages) RENESAS

39 / 75 page

DA9211 and DA9212

Datasheet

Revision 3.2

22-Feb-2022

CFR0011-120-00 Rev 3

39 of 74

Control Interfaces

All the features of DA9211 and DA9212 can be controlled by SW through a serial control interfaces.

The communication is selectable to be either a 2-WIRE (I2C compliant) or a 4-WIRE connection (SPI

compliant) via control IF_TYPE, which will be selected during the initial OTP read. If 4-WIRE is

selected, the GPIO3 and GPI4 are automatically configured as interface pins. Data is shifted into or

out of DA9211 and DA9212 under the control of the host processor, which also provides the serial

clock. In a normal application case the interface is only configured once from OTP values, which are

loaded during the initial start-up of DA9211 and DA9212.

DA9211 and DA9212 reacts only on read/write commands where the transmitted register address

(using the actual page bits as a MSB address range extensions) is within 0x50 to 0x67, 0xD0 to DF,

0x140 to 0x14F and (read only) 0x200 to 0x27F. Host access to registers outside these ranges will

be ignored. This means there will be no acknowledge after receiving the register address in 2-WIRE

Mode, and SO stays HI-Z in 4-WIRE Mode. During debug and production modes write access is

available to page 4 (0x200 to 0x27F). DA9211 and DA9212 will react only on write commands where

the transmitted register address is 0x00, 0x80, 0x100 to0x106. The host processor must read the

content of those registers before writing, thereby changing only the bit fields that are not marked as

reserved (the content of the read back comes from the compatible PMIC, for example DA9063).

If the STAND_ALONE bit is asserted (OTP bit), DA9211 and DA9212 will also react to read

commands.

4-WIRE Communication

In 4-WIRE Mode the interface uses a chip-select line (nCS/nSS), a clock line (SK), data input (SI)

and data output line (SO).

The DA9211 and DA9212 register map is split into four pages that each contain up to 128 registers.

The register at address zero on each page is used as a page control register. The default active

page after turn-on includes registers 0x50 to 0x6F. Writing to the page control register changes the

active page for all subsequent read/write operations unless an automatic return to page 0 was

selected by asserting bit REVERT. Unless the REVERT bit was asserted after modifying the active

page, it is recommended to read back the page control register to ensure that future data exchange

is accessing the intended registers.

All registers outside the DA9211 and DA9212 range are write only, that is, the DA9211 and DA9212

will not answer to a read command and the data bus is tri-state (they are implicitly directed to

DA9063). In particular the information contained in registers 0x105 and 0x106 is used by DA9211

and DA9212 to configure the control interface. They must be the same as the main PMIC (DA9063),

so that a write to those registers configures both the main PMIC and DA9211 and DA9212 at the

same time. The default OTP settings also need to be identical for a correct operation of the system.

The 4-WIRE interface features a half-duplex operation, that is, data can be transmitted and received

within a single 16-bit frame at enhanced clock speed (up to 14 MHz). It operates at the clock

frequencies provided by the host.

DA9211 Datasheet(PDF) 39 Page - Renesas Technology Corp

DA9211 Datasheet(HTML) 39 Page - Renesas Technology Corp

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