DA9211 datasheet(40/75 Pages) RENESAS

40 / 75 page

DA9211 and DA9212

Datasheet

Revision 3.2

22-Feb-2022

CFR0011-120-00 Rev 3

40 of 74

PMIC

(slave)

Host

processor

nCS/nSS

VDDIO

Slave device

nCS/nSS

VDDIO

4-WIRE interface

Host

processor

PMIC

Peripheral

device

Peripheral

device

SDA

SCL

SDA

VDDIO

2-WIRE interface

Figure 37: Schematic of 4-WIRE and 2-WIRE Power Manager Bus

A transmission begins when initiated by the host. Reading and writing is accomplished by the use of

an 8-bit command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host

begins shifting in on the SI pin under the control of the serial clock SK provided from the host. The

first seven bits specify the register address (0x01 to 0x07) that will be written or read by the host. The

word ends with an R/W bit, which together with the control bit R/W_POL specifies the direction of the

following data exchange. During register writing the host continues sending out data during the

following eight SK clocks. For reading, the host stops transmitting and the 8-bit register is clocked out

of DA9211 and DA9212 during the consecutive eight SK clocks of the frame. Address and data are

transmitted with MSB first. The polarity (active state) of nCS is defined by control bit nCS_POL. nCS

resets the interface when inactive and it has to be released between successive cycles.

The SO output from DA9211 and DA9212 is normally in high-impedance state and active only during

the second half of read cycles. A pull-up or pull-down resistor may be needed at the SO line if a

floating logic signal can cause unintended current consumption inside other circuits.

Table 13: 4-WIRE Clock Configurations

Configurations

CPHA clock

polarity

CPOL clock

phase

Output data is updated at SK

edge

Input data is registered at SK

edge

0 (idle low)

Falling

Rising

0 (idle low)

Rising

Falling

1 (idle high)

Rising

Falling

1 (idle high)

Falling

Rising

DA9211 and DA9212

’s 4-WIRE interface offers two further configuration bits. Clock polarity (CPOL)

and clock phase (CPHA) define when the interface will latch the serial data bits. CPOL determines

whether SK idles high (CPOL = 1) or low (CPOL = 0). CPHA determines on which SK edge data is

shifted in and out. With CPOL = 0 and CPHA = 0, DA9211 and DA9212 latch data on the SK rising

edge. If the CPHA is set to 1 the data is latched on the SK falling edge. CPOL and CPHA states

allow four different combinations of clock polarity and phase. Each setting is incompatible with the

other three. The host and DA9211 and DA9212 must be set to the same CPOL and CPHA states to

communicate with each other.

DA9211 Datasheet(PDF) 40 Page - Renesas Technology Corp

DA9211 Datasheet(HTML) 40 Page - Renesas Technology Corp

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