AD9389SLASHPCB datasheet(7/48 Pages) AD

7 / 48 page

AD9389

Rev. 0 | Page 7 of 48

Pin Type

Pin No.

Mnemonic

Description

Value

31, 30

Tx0+

Differential Output Channel 0

TMDS

Tx0−

Differential Output Channel 0 Complement

INT

Interrupt

1.8 V CMOS

POWER SUPPLY

24, 29, 36, 41

AVDD

Output Power Supply

1.8 V

1, 61, 62, 63, 64

DVDD

Digital and I/O Power Supply

1.8 V

16, 19, 20, 21

PVDD

PLL Power Supply

1.8 V

15, 17, 18, 22,

26, 32, 39, 42,

43, 59, 60, 79,

GND

Ground

0 V

CONTROL

SDA

Serial Port Data I/O

3.3 V CMOS

SCL

Serial Port Data Clock (100 kHz Maximum)

3.3 V CMOS

DDSDA

Serial Port Data I/O to Receiver

3.3 V CMOS

DDCSCL

Serial Port Data Clock to Receiver

3.3 V CMOS

NO CONNECT

48, 49

No Connect.

Table 5. Pin Function Descriptions

Pin Mnemonic

Description

OUTPUTS

TxC+

Differential Clock Output at Pixel Clock Rate; Transition Minimized Differential Signaling (TMDS).

TxC−

Differential Clock Output Complement.

Tx2+

Differential Output of the Red Data at 10× the Pixel Clock Rate; TMDS.

Tx2−

Differential Red Output Complement.

Tx1+

Differential Output of the Green Data at 10× the Pixel Clock Rate; TMDS.

Tx1−

Differential Green Output Complement.

Tx0+

Differential Output of the Blue Data at 10× the Pixel Clock Rate; TMDS.

Tx0−

Differential Blue Output Complement.

INT

Interrupt.

SERIAL PORT (2-WIRE)

SDA

Serial Port Data I/O.

SCL

Serial Port Data Clock.

DDSDA

Serial Port Data I/O Master to Receiver.

DDCSCL

Serial Port Data Clock Master to Receiver.

For a full, functional description of the 2-wire serial register, refer to the 2-Wire Serial Control Port section.

INPUTS

D[23:0]

Digital Input in RGB or YCbCr Format.

CLK

Video Clock Input.

Data Enable for Video Data.

HSYNC

Horizontal Sync Input.

VSYNC

Vertical Sync Input. This is the input for vertical sync.

EXT_SW

Place an 887 Ω resistor (1% tolerance) between this pin and ground.

HPD

Hot Plug Detect. This indicates to the interface whether the receiver is connected.

S/PDIF

S/PDIF Audio Input. This is the audio input from a Sony/Philips Digital Interface.

MCLK

Audio Reference Clock. Can be set from 128 × fS to 512 × fS.

I2S[3:0]

I2S Audio Inputs. These represent the eight channels of audio (two per input) available through I2S.

I2S CLK

I2S Audio Clock.

LRCLK

Left/Right Channel Selection.

PD/A0

Power Down.

AD9389/PCB Datasheet(PDF) 7 Page - Analog Devices

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