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YCbCr 4:2:2 DDR (Double Data Rate) Formats (12 bits, 10 bits, or 8 bits) with Embedded Syncs, Input ID = 4

An input with YCbCr 4:2:2 DDR data and embedded syncs (ITU 656) can be selected by setting the input ID (0x15[3:1]) to 0b100. The

Input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The two input pin

assignment styles are shown in Table 14. The input style can be set in 0x16[3:2]. The order of data input is the order in the table (for

example, 12 bit data is accepted as: Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3).

Table 14.

Data[23:0]

Input Format

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Style 1

12-bit

Cb/Y/Cr/Y[11:4]

[3:0]

10-bit

Cb/Y/Cr/Y[9:2]

[1:0]

8-bit

Cb/Y/Cr/Y[7:0]

Style 2

12-bit

Cb/Y/Cr/Y[11:0]

10-bit

Cb/Y/Cr/Y[9:0]

8-bit

Cb/Y/Cr/Y[7:0]

Normal 4:4:4 Input Format (RGB or YCbCr) Clocked at Double Data Rate (DDR), Input ID = 5

An input with YCbCr 4:4:4 DDR data and separate syncs can be selected by setting the input ID (0x15[3:1]) to 0b011. The input CS

(0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The three input pin assignment

styles are shown in Table 15. The input style can be set in 0x16[3:2].

Table 15.

Data[23:0]

Input Format

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Style 1

G[3:0]

B[7:0]

RGB 4:4:4 (DDR)

R[7:0]

G[7:4]

Y[3:0]

Cb[7:0]

YCbCr 4:4:4 (DDR)

Cr[7:0]

Y[7:4]

Style 2

R[7:0]

G[7:4]

RGB 4:4:4 (DDR)

G[3:0]

B[7:0]

Cr[7:0]

Y[7:4]

YCbCr 4:4:4 (DDR)

Y[3:0]

Cb[7:0]

Style 3

Y[7:0]

Cb[7:4]

YCbCr 4:4:4 (DDR)

Cb[3:0]

Cr[7:0]