AD9389SLASHPCB datasheet(14/48 Pages) AD

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AD9389

Rev. 0 | Page 14 of 48

4:2:2 TO 4:4:4 DATA CONVERSION

DE GENERATION

The AD9389 has the ability to convert YCbCr video from 4:4:4

to 4:2:2 and 4:2:2 to 4:4:4. To convert from 4:4:4 to 4:2:2, the

video data goes through a filter first to remove any artificial

downsampling noise. To convert from 4:2:2 to 4:4:4, the

AD9389 utilizes either the zero-order upconversion (pixel

repetition) or first-order upconversion (linear interpolation).

The upconversion and downconversions are used when the

video output timing format does not match the video input

timing format. The video output format is set by Register

0x16[7:6]. The video input format is set by the video ID

(0x15[3:1]) and video color space (0x16[0]). The default mode

for upconversion is pixel repetition. To use linear interpolation,

set Register 0x17[2] to 1.

The AD9389 offers a choice of DE from an external pin, or an

internally generated DE. To activate the internal DE generation,

set Register 0x17[0] to 1. Registers 0x35 to 0x3A are used to

define the DE. 0x35 and 0x36[7:6] define the number of pixels

from the HS leading edge to the DE leading edge. 0x36[5:0] are

the number of HSYNCs between the leading edge of VS and

DE. 0x37[7:5] defines the difference of HS counts during VS

blanking for interlace video. 0x37[4:0] and 0x38[7:1] indicate

the width of the DE. 0x39 and 0x3A[7:4] are the number of

lines of active video (see Figure 4).

HSYNC AND VSYNC GENERATION

For video with embedded HSYNC and VSYNC, such as EAV

and SAV, found in ITU 656 format, it is necessary to reconstruct

HSYNC and VSYNC. This is done with registers 0x30 to 0x34.

0x30 and 0x31[7:6] specify the number of pixels between the

HSYNC leading edge and the trailing edge of DE. Register

0x31[5:0] and Register 0x32[7:4] are the duration of the

HSYNC in pixel clocks. 0x32[3:0] and 0x33[7:2] are the number

of HS pulses between the trailing edge of the last DE and the

leading edge of the VSYNC pulse. Register 0x33[1:0] and

0x34[7:0] are the duration of VSYNC in units of HSYNCs.

HSYNC and VSYNC polarity can be specified by setting

0x17[6] (for VSYNC) and 0x17[5] (for HSYNC).

HORIZONTAL SYNC, VERTICAL SYNC, AND DE

GENERATION

When transmitting video data across the TMDS interface, it

is necessary to have an HSYNC, VSYNC, and data enable (DE)

defined for the image. ITU-656 based sources have start of

active video (SAV) and end of active video (EAV) signals built

in, but the HSYNC and VSYNC must be generated (the DE is

implied by the SAV and EAV signals). Other sources (with

separate syncs) have HSYNC, VSYNC, and DE supplied at the

same time as the pixel data.

HS DELAY

R0x35, R0x36[7:6]

VS DELAY

R0x36[5:0]

WIDTH

R0x37[4:0], R0x38[7:1]

HEIGHT

R0x39, R0x3A[7:4]

ACTIVE

VIDEO

Figure 4. Active Video

a: HSYNC PLACEMENT

R0x30, R0x31[7:6]

b: HSYNC DURATION

R0x31[5:0], R0x32[7:4]

EAV

HSYNC

SAV

Figure 5. HSYNC Reconstruction

AD9389/PCB Datasheet(PDF) 14 Page - Analog Devices

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