AD9389SLASHPCB datasheet(16/48 Pages) AD

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AD9389

Rev. 0 | Page 16 of 48

AUDIO DATA CAPTURE

The AD9389 is capable of receiving audio data in either I2S or

S/PDIF format for packetization and transmission over the

HDMI interface.

I2S AUDIO

The AD9389 can accommodate from two to eight channels of I2S

audio at up to a 192 kHz sampling rate. Selection of I2S audio mode

(vs. S/PDIF) is set with 0x0A[4] = 0. The detected sampling

frequency (from 32 kHz to 192 kHz) can be read in 0x04[7:4]. The

output sampling frequency (from 32 kHz to 192 kHz) can be

selected with 0x15[7:4]. The number of channels and the specific

channels can be selected in 0x0C[5:2] and 0x50[7:5]. If all eight

channels (I2S0 to I2S3) are required, setting all bits or 0x0C[5:2] to 1

selects eight channels. If I2S0 only is needed, setting 0x0C[2] to 1

selects this. The placement of these packets with respect to their

output can be specified in Register 0x0E to Register 0x11. Default

settings place all channels in their respective position (I2S0 left

channel in Channel 0 left position, I2S3 right channel in Channel 3

right position), but this mapping is completely programmable.

The AD9389 supports standard I2S, left-justified I2S, and right-

justified I2S formats via 0x0C[1:0] and sample word lengths

between 16 bits and 24 bits (0x14[3:0]).

S/PDIF AUDIO

The AD9389 is capable of accepting two channel LPCM and

encoded audio up to a 192 kHz sampling rate via the S/PDIF.

S/PDIF audio input is selected by setting 0x0A[4] = 1. The

AD9389 is capable of accepting S/PDIF with or without an

MCLK input. When no MCLK is present, the AD9389 makes

the determination of the CTS value (N/CTS determines the

MCLK frequency).

CTS GENERATION

Audio data being carried across the HDMI link, which is driven

by a TMDS (video) clock only, does not retain the original

audio sample clock.

The task of recreating this clock at the sink is called audio clock

regeneration. There are a variety of clock regeneration methods

that can be implemented in an HDMI sink, each with a

different set of performance characteristics. The HDMI

specification does not attempt to define exactly how these

mechanisms operate. It does, however, present a possible

configuration and it does define the data items that the HDMI

source supplies to the HDMI sink in order to allow the HDMI

sink to adequately regenerate the audio clock. It also defines

how that data is generated. In many video source devices, the

audio and video clocks are generated from a common clock

(coherent clocks). In this situation, there exists a rational

(integer divided by integer) relationship between these two

clocks. The HDMI clock regeneration architecture can take

advantage of this rational relationship and can also work in an

environment where there is no such relationship between these

two clocks, that is, where the two clocks are truly asynchronous

or where their relationship is unknown.

Figure 8 shows the system architecture model used by HDMI

for audio clock regeneration. The source determines the

fractional relationship between the video clock and an audio

reference clock (128 × audio sample rate) and passes the

numerator and denominator for that fraction to the sink across

the HDMI link. The sink can then recreate the audio clock from

the TMDS clock by using a clock divider and a clock multiplier.

The exact relationship between the two clocks is

128 × fS = fTMDS_clock × N/CTS

The source determines the value of the numerator N as stated in

Section 7.2.1 of the HDMI specification. Typically, this value N

is used in a clock divider to generate an intermediate clock that

is slower than the 128 × fS clock by the factor N. The source

typically determines the value of the denominator cycle time

stamp (CTS) by counting the number of TMDS clocks in each

of the 128 × fS/N clocks.

DIVIDE

CTS

CTS1

TMDS

CLOCK

VIDEO CLOCK

128 ×

SINK DEVICE

SOURCE DEVICE

1N AND CTS VALUES ARE TRANSMITTED USING THE “AUDIO CLOCK REGENERATION”

PACKET. VIDEO CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

MULTIPLY

CYCLE

TIME

COUNTER

Figure 8. Audio Clock Regeneration

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