601 Hardware Specifications, Rev 3

3

Preliminary/Subject to Change without Notice

— Memory unit with a two-element read queue and a three-element write queue

— Run-time reordering of loads and stores

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— A 256-entry, two-way set-associative UTLB

— Four-entry BAT array providing 128-Kbyte to 8-Mbyte blocks

— Four-entry, first-level ITLB

— Hardware table search (caused by UTLB misses) through hashed page tables

— 52-bit virtual address; 32-bit physical address

•

Facilities for enhanced system performance

— Bus interface can run at integer factor of operating frequency

— A 64-bit split-transaction external data bus with burst transfers

— Support for address pipelining and limited out-of-order bus transactions

— Snooped copy-back queues for cache block (sector) copy-back operations

— Bus extensions for I/O controller interface operations

— Multiprocessing support features that include the following:

–

Hardware enforced, four-state cache coherency protocol (MESI)

–

Separate port into cache tags for bus snooping

1.2 General Parameters

Table 1 provides a summary of the general parameters of the 601 and 601v.

The “v” in 601v denotes that this processor operates at different power supply voltages than other versions

of the 601.

Table 1. General Parameters of the PowerPC 601 Microprocessor

Characteristic

50, 66, 80 MHz

100 MHz (601v)

Technology

0.65

µm CMOS

4-level metal

0.5

µm CMOS

5-level metal

Package

304-pin C4FP

Surface mount

304-pin C4FP

Surface mount

Power supplies

3.6 V (5%)

2.5 V

± 5% (core)

5.0 V

± 5% (I/O)

Chip size

10.95 mm x 10.95 mm

8.6 mm x 8.6 mm

Maximum input rating

Chip can sustain 50 mA

into any pin.

Chip can sustain 50 mA

into any pin.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com