601 Hardware Specifications, Rev 3

13

Preliminary/Subject to Change without Notice

Note: The diagram should only be referenced in regard to the edge-to-edge measurement of the timing

specifications. It is not intended as a functional description of the input and output signals. Refer to the

PowerPC 601 RISC Microprocessor User’s Manual for functional descriptions and their related diagrams for

device operation.

Figure 3. PowerPC 601 Microprocessor Output Timing Diagram

PCLK_EN

VM

VM

VM

VM

2X_PCLK

21.0

23.0

20.0

22.0

24

25

23.1

26

28

29

All other

ARTRY, SHD

ABB, DBB

output signals

TS, XATS

21.1

20.1

22.1

27

23.1

Freescale Semiconductor, Inc.

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