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MPC601EC Datasheet(PDF) 10 Page - NXP Semiconductors

Part # MPC601EC
Description  PowerPC 601™ RISC Microprocessor Hardware Specifications
PDF  24 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC601EC Datasheet(HTML) 10 Page - NXP Semiconductors

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10
601 Hardware Specifications, Rev 3
Preliminary/Subject to Change without Notice
1.3.2.2 Output AC Specifications
The output specifications of the 601 and 601v for both driving high and driving low depend on the capacitive
loading on each output and the drive capability enabled for that output. Additionally, the timing
specifications for outputs driving low depend on the voltage swing required to drive to 0.8 V
(either 5.5–0.8 V or 3.6–0.8 V).
Table 7 provides the output AC timing specifications (shown in Figure 3) as absolute values for a theoretical
0 pF load. In order to derive the actual timing specifications guaranteed for a given set of conditions
(capacitive loading, drive capability, and voltage swing), the loading factors provided in Table 6 must be
used. The actual specifications are defined as follows:
tpd (actual) = ttable + (loading factor *Cload)
where:
tpd (actual) = the specification guaranteed
ttable = the value from Table 7
Cload = the capacitive loading on that signal in the system (minimum of 20 pF must be used)
For example, if an output buffer for a 50-MHz device is driving a load of 100 pF, the output propagation
delay, due to the capacitive load, driving high would be calculated as follows:
tpd (actual) = 10.5 ns + (100 pF * 0.047 ns/pF) = 15.2 ns.
Table 6. Loading Factors for Output Signals
Loading Factor
for Selected
Buffer Size
50 MHz
66 MHz
80 MHz
100 MHz
(601v)
Normal1
Double2
Normal1
Double2
Normal1
Double2
Normal1
Double2
Driving low
(5.5 V to 0.8 V)
0.088
0.053
0.080
0.048
0.072
0.043
0.072
0.039
Driving low
(3.6 V to 0.8V)
0.060
0.036
0.055
0.033
0.051
0.030
0.049
0.029
Driving high
(0.0 V to 2.0 V)
0.047
0.028
0.042
0.025
0.037
0.022
0.035
0.018
Notes: 1. Normal mode means that SC_DRIVE is negated.
2. Double drive is only available for the following signals: ABB, DBB, SHD, ARTRY, TS, and XATS.
Double drive is enabled by strapping the SC_DRIVE pin to Vdd. (Double drive mode increases the
capacitive drive capability of the signal by enabling a second driver.)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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