6

601 Hardware Specifications, Rev 3

Preliminary/Subject to Change without Notice

1.3.2 PowerPC 601 Microprocessor AC Electrical Characteristics

This section provides the AC electrical characteristics for the 601 and 601v.

1.3.2.1 Input AC Specifications

Table 4 provides the clock AC timing specifications as defined in Figure 1.

Notes: 1. Actual minimum gated by real time clock frequency

2. Maximum allowable sum of cycle-to-cycle or long-term jitter

3. Guaranteed by design/characterization

4. PCLK_EN is measured from the 1.4 V level of the signal in question to the 1.4 V level of the input

2X_PCLK.

Table 4. Clock AC Timing Specifications

VddI/O = Nominal ± 5%, VddINT = 3.6 V ± 5% or 2.5 V ± 5% V (601v, 100 MHz), GND = 0 V dc, Tj MAX = 85 °C

Num

Characteristic

50 MHz

66 MHz

80 MHz

100 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Frequency of operation

rtc1

50

rtc1

66

rtc1

80

rtc1

100

MHz

2X_PCLK rising edge jitter

———————

±1502

ps

1

2X_PCLK cycle time

10

—

7.5

—

6.25

—

5.0

—

ns

2/1

2X_PCLK duty cycle

measured at 1.4 V

35

65

35

65

35

65

40

60

%

2a

2X_PCLK minimum pulse

width at 1.8 V

——————

1.453

—ns

2b

2X_PCLK minimum pulse

width at 0.6 V

——————

1.273

—ns

3

PCLK_EN setup to falling

edge of 2X_PCLK

0.84

—

0.74

—

0.74

—

0.74

—ns

4

PCLK_EN hold from falling

edge of 2X_PCLK

1.84

—

1.84

—

1.54

—

1.54

—ns

Freescale Semiconductor, Inc.

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