VPA2000 datasheet(16/25 Pages) RENESAS

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VPA2000

Product Data

March 11, 2010

If over-voltage is detected during normal operation, the

power N-channel MOSFET will turn off, and it will turn on

again when output voltage drops below the comparator

hysteretic level. On the other hand, if over-voltage is

detected during power up, the boost regulator will shut

down.

Figure 29. Over-voltage Protection

Besides over-voltage protection, the boost regulator has

an over-current protection to prevent excess current from

flowing into the power N-channel MOSFET. When the

inductor peak current is beyond the current limit level, the

N-channel MOSFET will shut down. Thus, during over-

current, the output voltage will be lower than the

programmed output voltage. Connecting the RLIM pin to

VIN will set the current limit level to its default value 2.35A.

The current limit level can be adjusted lower by placing a

resistor divider from VREF pin to ground, see Figure 28 for

details. Therefore, ILIM is calculated as:

(A)

REF

LIM

[3]

where VREF = 1.2V. For example, to set the current limit

level to 1A, choose R4 = 4.99k , so R3 will be 9.09k .

Figure 30. Inductor Current Waveforms

For stability, connect a 4.99k resistor, RC, in series with

a 6.8nF capacitor, CC, from COMP pin to ground.

The average inductor current is proportional to the boost

regulator output current. As the output current decreases,

the inductor current will eventually reach zero, and if the

output current is further decreased, the boost regulator will

operate in discontinuous conduction mode (DCM). The

output current level that results in DCM is approximately:













−

OUT

[4]

where fSW is the switching frequency of the boost regulator.

When the output current level is reduced even further, the

boost converter will skip pulses randomly in order to

maintain the output regulation. The pulse skipping feature

is inherent to the boost regulator, and it improves the light-

load efficiency due to the reduction of switching losses.

Negative Linear Regulator

The negative linear regulator provides the negative output

voltage (VGL) with a 2-phase operation. During the first

phase, when VSWN is equal to AVDD, the flying capacitors

CGLFLY and CVGLREG are charged up. During the second

phase, when VSWN is equal to 0V, it level shifts CGLFLY, and

CGLFLY and CGL are now connected in parallel. Thus, CGL

charges up to a negative voltage.

The voltage across CGLFLY and CVGLREG is controlled by the

N-channel MOSFET, and VGL is set by the external

resistor divider R9 and R10 with the following equation:

R10

-1.2V

VGL

[5]

Figure 31. Negative Linear Regulator Block Diagram

VPA2000 Datasheet(PDF) 16 Page - Renesas Technology Corp

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