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CS5920 Datasheet(PDF) 34 Page - Applied Micro Circuits Corporation |
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CS5920 Datasheet(HTML) 34 Page - Applied Micro Circuits Corporation |
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34 / 160 page  S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 34 Data Book Table 20. Add-On Bus General Pins Signal Type Description SYSRST# out System Reset. An active-low buffered PCI bus RST# output signal. The signal is asynchro- nous and can be asserted through software from the PCI host interface. BPCLK out Buffered PCI Clock. This output is a buffered form of the PCI bus clock and has all of the behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability). ADCLK in Add-On Clock. All internal S5920 Add-On bus logic is synchronous to this clock. The clock is asynchronous to the PCI bus logic unless connected to the BPCLK signal. IRQ# out Interrupt Request. This output signals to Add-On logic that a significant event has occurred as a result of activity within the S5920. ADDINT# in Add-On interrupt. When enabled and asserted, this input will cause a PCI bus interrupt by driving INTA# low. The input is level sensitive and can be driven by multiple sources. This signal is connected to an internal pull-up. FLT# in Float. Floats all S5920 output signals when asserted. This signal is connected to an internal pull-up Pin 149 X For factory use only. Must be left open. Pin 136 X For factory use only. Must be left open. Pin 135 X For factory use only. Must be left open. Pin 113 X For factory use only. Must be left open. Pin 29 X For factory use only. Must be left open. |
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