CS5920 datasheet(97/160 Pages) AMCC

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S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

PCI BUS INTERFACE

This section details various events which may occur

on the S5920 PCI bus interface. Since the S5920

functions as a target or slave device, signal timing

details are given for target transactions only.

PCI BUS TRANSACTIONS

Because the PCI bus utilizes multiplexed address/data

pins (AD[31:0]), every PCI bus transaction consists of

an address phase followed by a data phase. An

address phase is defined as the clock period in which

FRAME# transitions from inactive to active. During the

address phase, a bus command is driven by the initia-

tor on the C/BE[3:0]# signal pins. If the command

indicates a PCI read, the clock cycle following the

address phase is used to perform a “bus turn-around”

cycle. A turn-around cycle is a clock period in which

the address/data bus is not driven by an initiator or a

target device. This is used to avoid PCI bus conten-

tion. For a write command, a turn-around cycle is not

needed, and the bus goes directly from an address

phase to a data phase.

All PCI bus transactions consist of an address phase

followed by one or more data phases. During the one-

PCI-clock-long address phase, the bus address and

command information is latched into the S5920. The

number of data phases depends on how many data

transfers are desired or are possible within a given ini-

tiator-target pair. A data phase consists of at least one

PCI clock. FRAME# is deasserted to indicate that the

final data phase of a PCI cycle is occurring. Wait

states may be added to any data phase (each wait

state is one PCI clock).

The PCI bus command presented on the C/BE[3:0]#

pins during the address phase can represent 16 possi-

ble states. Table 1 lists the PCI commands and those

which are supported by the S5920. A “Yes” in the

“Supported by S5920” column in Table 1 indicates that

the S5920 device will assert the signal DEVSEL#

when that particular command is issued along with the

appropriate PCI address.

The completion or termination of a PCI cycle can be

signaled in several ways. In most cases, the comple-

tion of the final data phase is indicated by the

assertion of the ready signals from both the target

(TRDY#) and initiator (IRDY#) while FRAME# is inac-

tive. In some cases, the target is not able to continue

or support a burst transfer and will assert a STOP#

signal. This is referred to as a target disconnect. There

is also the case where an addressed device does not

exist, and the signal DEVSEL# is not driven. In this

case, the initiator is responsible for ending the cycle.

This is referred to as a master abort. The bus is

returned to the idle phase when both FRAME# and

IRDY# are deasserted.

Table 52. PCI Bus Commands

C/BE[3:0]#

Command Type

Supported

0000

Interrupt Acknowledge

0001

Special Cycle

0010

I/O Read

Yes

0011

I/O Write

Yes

0100

Reserved

0101

Reserved

0110

Memory Read

Yes

0111

Memory Write

Yes

1000

Reserved

1001

Reserved

1010

Configuration Read

Yes

1011

Configuration Write

Yes

1100

Memory Read Multiple

Yes 1

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