AD8191ASTZ datasheet(14/32 Pages) AD

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AD8191

Rev. 0 | Page 14 of 32

VTTO

50Ω

OPx

ONx

AVEE

DISABLE

IOUT

Figure 26. High Speed Output Simplified Schematic

The AD8191 requires output termination resistors when the

high speed outputs are enabled. Termination can be internal

and/or external. The internal terminations of the AD8191 are

enabled by programming the TX_PTO bit of the transmitter

settings register or by setting the PP_OTO pin of the parallel

control interface. The internal terminations of the AD8191

default to the setting indicated by PP_OTO upon reset. External

terminations can be provided either by on-board resistors or by

the input termination resistors of an HDMI/DVI receiver. If

both the internal terminations are enabled and external termi-

nations are present, set the output current level to 20 mA by

programming the TX_OCL bit of the transmitter settings

PP_OCL pin of the parallel control interface. The output

current level defaults to the level indicated by PP_OCL upon

reset. If only external terminations are provided (if the internal

terminations are disabled), set the output current level to 10 mA

by programming the TX_OCL bit of the transmitter settings

interface. The high speed outputs must be disabled if there are

no output termination resistors present in the system.

The output pre-emphasis can be manually configured to provide

one of four different levels of high frequency boost. The specific

boost level is selected by programming the TX_PE bits of the

transmitter settings register through the serial control interface,

or by setting the PP_PE bus of the parallel control interface. No

specific cable length is suggested for a particular pre-emphasis

setting because cable performance varies widely between

manufacturers.

HIGH SPEED (TMDS) SWITCHING MODES

The AD8191 has three high speed switching modes: quad, dual,

and single. These are selected by programming the HS_SM bits

of the high speed device modes register through the serial

control interface.

Quad Switching Mode

This is the default mode. In quad mode, the AD8191 behaves

like a 4:1 HDMI/DVI link multiplexer routing groups of four

TMDS input channels to the four-channel output. This mode is

accessible through both the serial and the parallel control

interfaces. When using the serial control interface, the user

selects which TMDS link is routed to the output by

programming the HS_CH bits of the high speed device modes

When using the parallel control interface, the user selects which

TMDS link is routed to the output by setting the PP_CH bus of

the parallel control interface in accordance with the switch

mapping listed in Table 26.

Dual Switching Mode

In this mode, the AD8191 behaves as a locked dual [8:1] TMDS

channel switch. The two 8:1 switches share the channel select

input and, therefore, switch together. The user selects which two

out of the eight possible input groups are routed to output by

programming the HS_CH bits of the high speed device modes

This mode is only accessible through the serial control interface.

Single Switching Mode

In this mode, the AD8191 behaves as a single 16:1 TMDS

channel multiplexer; one of the 16 input channels is routed to

all of the outputs. The user selects which input channel is

routed to the outputs by programming the HS_CH bits in the

high speed device modes register in accordance with the switch

mapping listed in Table 10. This mode is only accessible

through the serial control interface.

AUXILIARY SWITCH

The auxiliary (low speed) lines have no amplification. They are

routed using a passive switch that is bandwidth compatible with

standard speed I2C. The schematic equivalent for this passive

connection is shown in Figure 27.

AUX_COM0

AUX_A0

½CAUX

RAUX

Figure 27. Auxiliary Channel Simplified Schematic,

AUX_A0 to AUX_COM0 Routing Example

When turning off the AD8191, care needs to be taken with

the AMUXVCC supply to ensure that the auxiliary multiplexer

pins remain in a high impedance state. A scenario that illustrates

this requirement is one where the auxiliary multiplexer is used

to switch the display data channel (DDC) bus. In some applica-

tions, additional devices can be connected to the DDC bus

(such as an EEPROM with EDID information) upstream of the

AD8191. Extended display identification data (EDID) is a VESA

standard-defined data format for conveying display configuration

information to sources to optimize display use. EDID devices

may need to be available via the DDC bus, regardless of the

state of the AD8191 and any downstream circuit. For this

configuration, the auxiliary inputs of the powered down

AD8191 need to be in a high impedance state to avoid pulling

down on the DDC lines and preventing these other devices

from using the bus.

When the AD8191 is powered from a simple resistor network,

as shown in Figure 28, it uses the 5 V supply that is required

from any HDMI/DVI source to guarantee high impedance of

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