AD8191ASTZ datasheet(24/32 Pages) AD

24 / 32 page

AD8191

Rev. 0 | Page 24 of 32

RECEIVER SETTINGS REGISTER

High speed (TMDS) channels input termination is fixed to on

when using the parallel interface.

INPUT TERMINATION PULSE REGISTER 1 AND

High speed input (TMDS) channels pulse-on-source switching

fixed to off when using the parallel interface.

RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2

PP_EQ: High Speed (TMDS) Inputs Equalization Level

Select Bit (For All TMDS Input Channels)

The input equalization cannot be set individually (per channel)

when using the parallel interface; one equalization setting

affects all input channels.

Table 28. PP_EQ Description

PP_EQ

Description

Low equalization (6 dB)

High equalization (12 dB)

TRANSMITTER SETTINGS REGISTER

PP_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis

Level Select Bus (For All TMDS Channels)

Table 29. PP_PE[1:0] Description

PP_PE[1:0]

Description

No pre-emphasis (0 dB)

Low pre-emphasis (2 dB)

Medium pre-emphasis (4 dB)

High pre-emphasis (6 dB)

PP_OTO: High Speed (TMDS) Output Termination On/Off

Select Bit (For All TMDS Channels)

Table 30. PP_OTO Description

PP_OTO

Description

Output termination off

Output termination on

PP_OCL: High Speed (TMDS) Output Current Level Select

Bit (For All TMDS Channels)

Table 31. TX_OCL Description

PP_OCL

Description

Output current set to 10 mA

Output current set to 20 mA

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