AD8191ASTZ datasheet(16/32 Pages) AD

16 / 32 page

AD8191

Rev. 0 | Page 16 of 32

SERIAL CONTROL INTERFACE

RESET

On initial power-up, or at any point in operation, the AD8191

pulling the RESET pin to low in accordance with the specifica-

tions in Table 1. During normal operation, however, the RESET

pin must be pulled up to 3.3 V. Following a reset, the prepro-

grammed default values of the AD8191 register set correspond

to the state of the parallel interface configuration registers, as

listed in Table 24. The AD8191 can be controlled through the

parallel control interface until the first serial control event

occurs. As soon as any serial control event occurs, the serial

programming values, corresponding to the state of the serial

interface configuration registers (Table 5), override any prior

parallel programming values, and the parallel control interface

is disabled until the part is subsequently reset.

WRITE PROCEDURE

To write data to the AD8191 register set, an I2C master (such as

a microcontroller) needs to send the appropriate control signals

to the AD8191 slave device. The signals are controlled by the

I2C master, unless otherwise specified. For a diagram of the

procedure, see Figure 29. The steps for a write procedure are as

follows:

Send a start condition (while holding the I2C_SCL line

high, pull the I2C_SDA line low).

Send the AD8191 part address (seven bits). The upper four

bits of the AD8191 part address are the static value [1001]

and the three LSBs are set by Input Pin I2C_ADDR2, Input

Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). This

transfer should be MSB first.

Send the write indicator bit (0).

Wait for the AD8191 to acknowledge the request.

Send the register address (eight bits) to which data is to be

written. This transfer should be MSB first.

Wait for the AD8191 to acknowledge the request.

Send the data (eight bits) to be written to the register

whose address was set in Step 5. This transfer should be

MSB first.

Wait for the AD8191 to acknowledge the request.

Perform one of the following:

9a. Send a stop condition (while holding the I2C_SCL

line high, pull the I2C_SDA line high) and release

control of the bus to end the transaction (shown in

Figure 29).

9b. Send a repeated start condition (while holding the

I2C_SCL line high, pull the I2C_SDA line low) and

continue with Step 2 in this procedure to perform

another write.

9c. Send a repeated start condition (while holding the

I2C_SCL line high, pull the I2C_SDA line low) and

continue with Step 2 of the read procedure (in the

Read Procedure section) to perform a read from

another address.

9d. Send a repeated start condition (while holding the

I2C_SCL line high, pull the I2C_SDA line low) and

continue with Step 8 of the read procedure (in the

Read Procedure section) to perform a read from the

same address set in Step 5.

R/W

ACK

ADDR

START

FIXED PART

ADDR

DATA

STOP

ACK

I2C_SCL

GENERAL CASE

I2C_SDA

EXAMPLE

I2C_SDA

*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE

LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.

Figure 29. I2C Write Diagram

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