AD8191

Rev. 0 | Page 23 of 32

PARALLEL INTERFACE CONFIGURATION REGISTERS

The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and

PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface.

The state of each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).

Table 24. Parallel Interface Register Map

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

High speed

switch enable

High speed switching

mode select (quad)

High speed source select

High Speed

Device Modes

PP_EN

0

0

0

0

PP_CH[1]

PP_CH[0]

Auxiliary

switch enable

Auxiliary switching

mode select (quad)

Auxiliary switch source select

Auxiliary Device

Modes

1

0

0

0

0

PP_CH[1]

PP_CH[0]

Input term. on/off

select (termination

always on)

Receiver

Settings

1

Source A and Source B input termination pulse-on-source switch select (termination always on)

Input

Termination

Pulse 1

0

0

0

0

0

0

0

0

Source C and Source D input termination pulse-on-source switch select (termination always on)

Input

Termination

Pulse 2

0

0

0

0

0

0

0

0

Source A and Source B input equalization level select

Receive

Equalizer 1

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

Source C and Source D input equalization level select

Receive

Equalizer 2

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

Output pre-emphasis

level select

Output

termination

on/off select

Output current level

select

Transmitter

Settings

PP_PE[1]

PP_PE[0]

PP_OTO

PP_OCL

HIGH SPEED DEVICE MODES REGISTER

The high speed (TMDS) switching mode is fixed to quad mode

when using the parallel interface.

PP_EN: High Speed (TMDS) Channels Enable Bit

Table 25. PP_EN Description

PP_EN

Description

0

High speed channels off, low power/standby mode

1

High speed channels on

PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus

Table 26. Quad High speed Switch Mode Mapping

PP_CH[1:0]

O[3:0]

Description

00

A[3:0]

High Speed Source A switched to

output

01

B[3:0]

High Speed Source B switched to

output

10

C[3:0]

High Speed Source C switched to

output

11

D[3:0]

High Speed Source D switched to

output

AUXILIARY DEVICE MODES REGISTER

The auxiliary (low speed) switch is always enabled and the

auxiliary switching mode is fixed to quad mode when using the

parallel interface.

PP_CH[1:0]: Auxiliary Switch Source Select Bus

Table 27. Quad Auxiliary Switch Mode Mapping

PP_CH[1:0]

AUX_COM[3:0]

Description

00

AUX_A[3:0]

Auxiliary Source A switched to

output

01

AUX_B[3:0]0

Auxiliary Source B switched to

output

10

AUX_C[3:0]

Auxiliary Source C switched to

output

11

AUX_D[3:0]

Auxiliary Source D switched to

output