AD8191ASTZ datasheet(28/32 Pages) AD

28 / 32 page

AD8191

Rev. 0 | Page 28 of 32

PCB DIELECTRIC

LAYER 1: SIGNAL (MICROSTRIP)

SILKSCREEN

PCB DIELECTRIC

LAYER 2: GND (REFERENCE PLANE)

LAYER 3: PWR (REFERENCE PLANE)

LAYER 4: SIGNAL (MICROSTRIP)

REFERENCE LAYER

RELIEVED UNDERNEATH

MICROSTRIP

Figure 32. Example Board Stackup

HPD is a dc signal presented by a sink to a source to indicate

that the source EDID is available for reading. The placement

of this signal is not critical, but it should be routed as directly

as possible.

When the AD8191 is powered up, one set of the auxiliary in-

puts is passively routed to the outputs. In this state, the AD8191

looks like a 100 Ω resistor between the selected auxiliary inputs

and the corresponding outputs as illustrated in Figure 27. The

AD8191 does not buffer the auxiliary signals, therefore, the

input traces, output traces, and the connection through the

AD8191 all must be considered when designing a PCB to meet

HDMI/DVI specifications. The unselected auxiliary inputs of the

AD8191 are placed into a high impedance mode when the device

is powered up. To ensure that all of the auxiliary inputs of the

AD8191 are in a high impedance mode when the device is powered

off, it is necessary to power the AMUXVCC supply as illustrated

in Figure 28.

In contrast to the auxiliary signals, the AD8191 buffers the

TMDS signals, allowing a PCB designer to layout the TMDS

inputs independently of the outputs.

Power Supplies

The AD8191 has five separate power supplies referenced to

two separate grounds. The supply/ground pairs are:

•

AVCC/AVEE

•

VTTI/AVEE

•

VTTO/AVEE

•

DVCC/DVEE

•

AMUXVCC/DVEE

The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies

power the core of the AD8191. The VTTI/AVEE supply (3.3 V)

powers the input termination (see Figure 25). Similarly, the

VTTO/AVEE supply (3.3 V) powers the output termination

(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)

powers the auxiliary multiplexer core and determines the

maximum allowed voltage on the auxiliary lines. For example,

if the DDC bus is using 5 V I2C, then AMUXVCC should be

connected to +5 V relative to DVEE.

In a typical application, all pins labeled AVEE or DVEE should

be connected directly to ground. All pins labeled AVCC,

DVCC, VTTI, or VTTO should be connected to 3.3 V, and

Pin AMUXVCC tied to 5 V. The supplies can also be powered

individually, but care must be taken to ensure that each stage of

the AD8191 is powered correctly.

Power Supply Bypassing

The AD8191 requires minimal supply bypassing. When

powering the supplies individually, place a 0.01 μF capacitor

between each 3.3 V supply pin (AVCC, DVCC, VTTI, and

VTTO) and ground to filter out supply noise. Generally, bypass

capacitors should be placed near the power pins and should

connect directly to the relevant supplies (without long inter-

vening traces). For example, to improve the parasitic inductance

of the power supply decoupling capacitors, minimize the trace

length between capacitor landing pads and the vias as shown in

Figure 33.

EXTRA ADDED INDUCTANCE

RECOMMENDED

NOT RECOMMENDED

Figure 33. Recommended Pad Outline for Bypass Capacitors

AD8191ASTZ Datasheet(PDF) 28 Page - Analog Devices

AD8191ASTZ Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL