AD8191ASTZ datasheet(27/32 Pages) AD

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AD8191

Rev. 0 | Page 27 of 32

pair. Furthermore, to prevent unwanted signal coupling and

interference, route the TMDS signals away from other signals

and noise sources on the PCB.

Both traces of a given differential pair must be equal in length

to minimize intrapair skew. Maintaining the physical symmetry

of a differential pair is integral to ensuring its signal integrity;

excessive intrapair skew can introduce jitter through duty cycle

distortion (DCD). The p and n of a given differential pair should

always be routed together to establish the required 100 Ω differ-

ential impedance. Enough space should be left between the

differential pairs of a given group so that the n of one pair does

not couple to the p of another pair. For example, one technique is

to make the interpair distance 4 to 10 times wider than the

intrapair spacing.

Any group of four TMDS channels (Input A, Input B, Input C,

Input D, or the output) should have closely matched trace

lengths to minimize interpair skew. Severe interpair skew can

cause the data on the four different channels of a group to arrive

out of alignment with one another. A good practice is to match

the trace lengths for a given group of four channels to within

0.05 inches on FR4 material.

The length of the TMDS traces should be minimized to reduce

overall signal degradation. Commonly used PC board material,

such as FR4, is lossy at high frequencies; therefore, long traces

on the circuit board increase signal attenuation resulting in

decreased signal swing and increased jitter through intersymbol

interference (ISI).

Controlling the Characteristic Impedance of a TMDS

Differential Pair

The characteristic impedance of a differential pair depends on

a number of variables including the trace width, the distance

between the two traces, the height of the dielectric material

between the trace and the reference plane below it, and the

dielectric constant of the PCB binder material. To a lesser

extent, the characteristic impedance also depends upon the

trace thickness and the presence of solder mask. There are

many combinations that can produce the correct characteristic

impedance. It is generally required to work with the PC board

fabricator to obtain a set of parameters to produce the desired

results.

One consideration is how to guarantee a differential pair with

a differential impedance of 100 Ω over the entire length of the

trace. One technique to accomplish this is to change the width

of the traces in a differential pair based on how closely one trace

is coupled to the other. When the two traces of a differential

pair are close and strongly coupled, they should have a width

that produces a 100 Ω differential impedance. When the traces

split apart, to go into a connector, for example, and are no

longer so strongly coupled, the width of the traces should be

increased to yield a differential impedance of 100 Ω in the new

configuration.

TMDS Terminations

The AD8191 provides internal, 50 Ω single-ended terminations

for all of its high speed inputs and outputs. It is not necessary to

include external termination resistors for the TMDS differential

pairs on the PCB.

The output termination resistors of the AD8191 back-terminate

the output TMDS transmission lines. These back-terminations

act to absorb reflections from impedance discontinuities on the

output traces, improving the signal integrity of the output traces

and adding flexibility to how the output traces can be routed.

For example, interlayer vias can be used to route the AD8191

TMDS outputs on multiple layers of the PCB without severely

degrading the quality of the output signal.

Auxiliary Control Signals

There are four single-ended control signals associated with each

source or sink in an HDMI/DVI application. These are hot plug

detect (HPD), consumer electronics control (CEC), and two

display data channel (DDC) lines. The two signals on the DDC

bus are SDA and SCL (serial data and serial clock, respectively).

These four signals can be switched through the auxiliary bus of

the AD8191 and do not need to be routed with the same strict

considerations as the high speed TMDS signals.

In general, it is sufficient to route each auxiliary signal as a

single-ended trace. These signals are not sensitive to impedance

discontinuities, do not require a reference plane, and can be

routed on multiple layers of the PCB. However, it is best to

follow strict layout practices whenever possible to prevent the

PCB design from affecting the overall application. The specific

routing of the HPD, CEC, and DDC lines depends upon the

application in which the AD8191 is being used.

For example, the maximum speed of signals present on the

auxiliary lines is 100 kHz I2C data on the DDC lines; therefore,

any layout that enables 100 kHz I2C to be passed over the DDC

bus should suffice. The HDMI 1.2a specification, however,

places a strict 50 pF limit on the amount of capacitance that can

be measured on either SDA or SCL at the HDMI input connector.

This 50 pF limit includes the HDMI connector, the PCB, and

whatever capacitance is seen at the input of the AD8191, or an

equivalent receiver. There is a similar limit of 100 pF of input

capacitance for the CEC line.

The parasitic capacitance of traces on a PCB increases with

trace length. To help ensure that a design satisfies the HDMI

specification, the length of the CEC and DDC lines on the PCB

should be made as short as possible. Additionally, if there is a

reference plane in the layer adjacent to the auxiliary traces in

the PCB stack-up, relieving or clearing out this reference plane

immediately under the auxiliary traces significantly decreases

the amount of parasitic trace capacitance. An example of the

board stackup is shown in Figure 32.

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