ADP3196 datasheet(10/20 Pages) AD

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ADP3196

Rev. 0 | Page 10 of 20

THEORY OF OPERATION

The ADP3196 combines a multimode, fixed frequency PWM

control with multiphase logic outputs for use in 2-, 3-, and

4-phase synchronous buck CPU core supply power converters.

The internal VID DAC is designed to interface with the AMD

6-bit CPUs.

Multiphase operation is important for producing the high

currents and low voltages demanded by today’s microprocessors.

Handling the high currents in a single-phase converter places

high thermal demands on the components in the system, such

as the inductors and MOSFETs.

The multimode control of the ADP3196 ensures a stable, high

performance topology for the following:

•

Balancing currents and thermals between phases

•

High speed response at the lowest possible switching

frequency and output decoupling

•

Minimizing thermal switching losses by utilizing lower

frequency operation

•

Tight load line regulation and accuracy

•

High current output due to 4-phase operation

•

Reduced output ripple due to multiphase cancellation

•

PC board layout noise immunity

•

Ease of use and design due to independent component

selection

•

Flexibility in operation for tailoring design to low cost or

high performance

START-UP SEQUENCE

The ADP3196 follows the start-up sequence shown in Figure 7.

After both the EN and UVLO conditions are met, the DELAY pin

goes through one cycle (TD1). The first four clock cycles of TD2

are blanked from the PWM outputs and used for phase detection as

explained in the Phase Detection Sequence section. Then, the soft

start ramp is enabled (TD2) and the output comes up to the

programmed DAC Voltage.

After TD2 has been completed and the PWRGD masking time

(equal to VID on-the-fly masking) is finished, a second ramp

on the DELAY pin sets the PWRGD blanking (TD3).

ADP3196 EN

VCC_CORE

DELAY

VR READY

(ADP3196 PWRGD)

CPU

VID INPUTS

TD1

TD2

TD3

0.8V

VDELAY(TH)

(1.7V)

VVID

SUPPLY

UVLO

THRESHOLD

VID INVALID

VID VALID

Figure 7. System Start-Up Sequence

PHASE DETECTION SEQUENCE

During startup, the number of operational phases and their

phase relationship is determined by the internal circuitry that

monitors the PWM outputs. Normally, the ADP3196 operates

as a 4-phase PWM controller. Connecting the PWM4 pin to the

VCC pin programs 3-phase operation while connecting the

PWM4 pin and the PWM3 pin to the VCC pin programs

2-phase operation.

While EN is low and prior to soft start, Pins PWM3 and PWM4

sink approximately 100 µA. An internal comparator checks the

voltage of each pin vs. a threshold of 3 V. If the pin is tied to

VCC, it is above the threshold. Otherwise, an internal current

sink pulls the pin to GND, which is below the threshold. PWM1

and PWM2 are low during the phase detection interval, which

occurs during the first four clock cycles of TD2. After this time,

if the remaining PWM outputs are not pulled to VCC, the

100 µA current sink is removed and they function as normal

PWM outputs. If they are pulled to VCC, the 100 µA current

source is removed and the outputs are put into a high

impedance state.

The PWM outputs are logic-level devices intended for driving

external gate drivers, such as the ADP3120A. Because each

phase is monitored independently, operation approaching 100%

duty cycle is possible. In addition, more than one output can be

on at the same time to allow overlapping phases.

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