XDP710 datasheet(49/85 Pages) INFINEON

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Input voltage suddenly increases generating a certain VDS meanwhile the output cap is charged up to the

new voltage level

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RDSON is too high

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During I_REG state after an OC event, VDS has to increase too much in order to keep the current at an

appropriate level

In this scenario, the SOAD_TMR[1:0] deglitch timer starts. If FET VDS and IDS go back within the SOA limits before

the timer expires, the system continues normal operation in ON state. Otherwise the SOAR_TMR[2:0] regulation

timer starts while the system continues to regulate the current to stay within the SOA limits. If SOAR condition

is cleared before this second timer expires, system goes back to ON state. If it persists, a SOA regulation fault is

triggered and FET is opened with a regular pull-down.

If the regulated current through the FET goes below a level of 1 A, regulation stops, FET is turned off and a SOAR

fault is declared.

The system will retry power-up after a cool down period according to RETRY command settings.

Note: The SOAR fault disabling means that a fault is never triggered and FET is never turned off in case of a SOA

limits violation. It is recommended to keep the SOAR fault enabled for safety reasons.

Overtemperature (OT) Fault

If, during STANDBY, INIT_SOA_REG, normal operation or FAULT, the temperature measured between the TSNS_P

and TSNS_N pins raises above the OT_FAULT_LIMIT value, a fault is triggered and FET is opened with a regular

pull-down.

XDP710 waits until FET is completely turned off, then keeps monitoring the FET temperature and stays in the

FAULT state until it drops below OT_FAULT_LIMIT - 12°C. In this case, the power-up sequence initiates, FAULT pin

deasserts and PWRGD pin asserts as soon as the necessary conditions are met.

On-chip Thermal Shut-down (TSD) Fault

XDP710 has an on-chip temperature sensor with a programmable fault limit of TTS_UTH. If die temperature

exceeds this value, a fault is triggered and FET is opened with a regular pull-down. XDP710 waits until FET is

completely turned-off, then remains idle in the FAULT state until the temperature drops below TTS_LTH (which is

equivalent to TTS_UTH - 10°C), at which point the power-up procedure is started.

4.2.6

Power-up faults

Unsuccessful Power-up (Watchdog, WD) Fault

The watchdog timer can be configured from 10 ms to 10000 ms by means of the WATCHDOG[2:0] bits. Its

configurable steps are compliant with common SOA lines so that protection can be implemented according to

the maximum allowed timer for a specific VDS vs IDS scenario. It starts running as soon as power-up procedure

starts in the INIT_SOA_REG state. If FET is not fully enhanced (VDS < 1.0 V and VGS > 7.8 V) before the timer

expires, a WD fault is triggered and FET is turned-off with a regular pull-down.

A power-up is retried according to the RETRY command settings, in which case, the FAULT pin is cleared when

leaving FAULT state before any retry attempt. The corresponding status bit remains set until it is manually

cleared or device is restarted or power cycled.

Unsuccessful Retry (UR) Fault

The UR fault can only occur in FAULT state when the retry counter expires after one of the retry fault events

(SOC, OUV, WD, OC, SOAR). The retry counter decrements on each retry event. If it reaches a value of zero

XDP710 Hot-swap Controller

Wide input voltage range (5.5 V to 80 V) system monitoring and protection IC

4 Product Features

Datasheet

Rev. 2.0

2022-11-22

XDP710 Datasheet(PDF) 49 Page - Infineon Technologies AG

XDP710 Datasheet(HTML) 49 Page - Infineon Technologies AG

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