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5. Flash Management

5.1 Error Correction/Detection

PV910-M280 implements a hardware ECC scheme, based on the Low Density Parity Check (LDPC).

LDPC is a class of linear block error correcting code which has apparent coding gain over BCH code

because LDPC code includes both hard decoding and soft decoding algorithms. With the error rate

decreasing, LDPC can extend SSD endurance and increase data reliability while reading raw data

inside a flash chip.

5.2 Bad Block Management

Current production technology is unable to guarantee total reliability of NAND flash memory array.

When a flash memory device leaves factory, it comes with a minimal number of initial bad blocks

during production or out-of-factory as there is no currently known technology that produce flash chips

free of bad blocks. In addition, bad blocks may develop during program/erase cycles. Since bad

blocks are inevitable, the solution is to keep them in control. Apacer flash devices are programmed

with ECC, page mapping technique and S.M.A.R.T to reduce invalidity or error. Once bad blocks are

detected, data in those blocks will be transferred to free blocks and error will be corrected by

designated algorithms.

5.3 Global Wear Leveling

Flash memory devices differ from Hard Disk Drives (HDDs) in terms of how blocks are utilized. For

HDDs, when a change is made to stored data, like erase or update, the controller mechanism on

HDDs will perform overwrites on blocks. Unlike HDDs, flash blocks cannot be overwritten and each

P/E cycle wears down the lifespan of blocks gradually. Repeatedly program/erase cycles performed

on the same memory cells will eventually cause some blocks to age faster than others. This would

bring flash storages to their end of service term sooner. Global wear leveling is an important

mechanism that levels out the wearing of all blocks so that the wearing-down of all blocks can be

almost evenly distributed. This will increase the lifespan of SSDs.

5.4 Flash Translation Layer

– Page Mapping

Page mapping is an advanced flash management technology whose essence lies in the ability to

gather data, distribute the data into flash pages automatically, and then schedule the data to be

evenly written. Page-level mapping uses one page as the unit of mapping. The most important

characteristic is that each logical page can be mapped to any physical page on the flash memory

device. This mapping algorithm allows different sizes of data to be written to a block as if the data is

written to a data pool and it does not need to take extra operations to process a write command. Thus,

page mapping is adopted to increase random access speed and improve SSD lifespan, reduce block

erase frequency, and achieve optimized performance and lifespan.