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S29CD032J Datasheet(PDF) 56 Page - SPANSION |
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S29CD032J Datasheet(HTML) 56 Page - SPANSION |
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56 / 76 page ![]() 54 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Pre limin ar y) 18.3 Synchronous Operations Notes 1. Using the max tAAVS and min tADVCS specs together will result in incorrect data output. 2. Not 100% tested 3. Recommended 50% Duty Cycle Table 18.3 Burst Mode Read for 32 Mb and 16 Mb Parameter Description Speed Options Unit JEDEC Std. 75MHz, OR 66MHz, OP 56MHz, OM 40MHz, OJ tBACC Burst Access Time Valid Clock to Output Delay Max 7.5 FBGA 8 8 8 ns tADVCS ADV# Setup Time to Rising Edge of CLK Min 6666 ns tADVCH ADV# Hold Time from Rising Edge of CLK Min 1.5 ns tADVP ADV# Pulse Width Min 7.5 8.5 9.5 10.5 ns tBDH Valid Data Hold from CLK (Note 2) Min 2233 ns tINDS CLK to Valid IND/WAIT# (Note 2) Max 7.5 FBGA 9 FBGA 9.5 PQFP 10 FBGA 10 PQFP 17 ns tINDH IND/WAIT# Hold from CLK (Note 2) Min 2233 ns tIACC ADV or ADD Valid (Whichever Occurs Last) to Valid Data Out, Initial Burst Access Max 48545454 ns tCLK CLK Period Min 13.3 15.15 17.85 25 ns Max 60 tCR CLK Rise Time (Note 2) Max 3 ns tCF CLK Fall Time (Note 2) Max 3 ns tCLKH CLK High Time (Note 3) Min 6.65 6.8 8.0 11.25 ns tCLKL CLK Low Time (Note 3) Min 6.65 272727 ns tOE Output Enable to Output Valid Max 20 20 ns tDF tOEZ Output Enable to Output High Z (Note 2) Min 2233 ns Max 7.5 10 15 17 tEHQZ tCEZ Chip Enable to Output High Z (Note 2) Max 7.5 10 15 17 ns tCES CE# Setup Time to Clock Min 4456 ns tAAVS ADV# Falling Edge to Address Valid (Note 1) Max 6.5 6.5 6.5 6.5 ns tAAVH Address Hold Time from Rising Edge of AVD# Min 15 15 15 15 ns tRSTZ RESET# Low to Output High Z (Note 2) Max 7.5 10 15 17 ns tWADVH1 ADV# Falling Edge to WE# Falling Edge Min 5555 ns tWADVH2 ADV# Rising Edge to WE# Rising Edge Min 10 10 10 10 ns |
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