FSDH321, FSDL321

www.onsemi.com

8

FUNCTIONAL DESCRIPTION

Startup

In previous generations of Power Switches the Vstr pin

had an external resistor to the DC input voltage line. In this

generation the startup resistor is replaced by an internal high

voltage current source and a switch that shuts off when

15 ms goes by after the supply voltage, Vcc, gets above 12 V.

The source turns back on if Vcc drops below 8 V.

Figure 14. High Voltage Current Source

Vin, dc

ISTR

Vstr

Vcc

J−FET

ICH

Vcc < 8 V

UVLO on

15 ms after

Vcc

≥ 12 V

UVLO off

Feedback Control

The FSDx321 employs current mode control, as shown in

Figure 15. An opto−coupler (such as the H11A817A) and

shunt regulator (such as the KA431) are typically used to

implement the feedback network. Comparing the feedback

voltage with the voltage across the Rsense resistor plus an

offset voltage makes it possible to control the switching duty

cycle. When the KA431 reference pin voltage exceeds the

internal reference voltage of 2.5 V, the optocoupler LED

current increases, the feedback voltage Vfb is pulled down

and it reduces the duty cycle. This event typically happens

when the input voltage is increased or the output load is

decreased.

Figure 15. Pulse Width Modulation (PWM) Circuit

Vo

431

Vfb

3

CFB

+

−

VFB

5 uA

0.9 mA

Vcc

Vcc

OSC

VSD

OLP

D1

D2

2.5R

R

−

+

Gate

driver

+

−

VFB,in

Leading Edge Blanking (LEB)

At the instant the internal SENSEFET is turned on, the

primary side capacitance and secondary side rectifier diode

reverse recovery typically cause a high current spike

through the SENSEFET. Excessive voltage across the

Rsense resistor leads to incorrect feedback operation in the

current mode PWM control. To counter this effect, the

power switch employs a leading edge blanking (LEB)

circuit. This circuit inhibits the PWM comparator for a short

time (tLEB) after the SENSEFET is turned on.

Protection Circuits

The power switch has several protective functions such as

over load protection (OLP), over voltage protection (OVP),

abnormal over current protection (AOCP), under voltage

lock out (UVLO) and thermal shutdown (TSD). Because

these protection circuits are fully integrated inside the IC

without external components, the reliability is improved

without increasing cost. Once a fault condition occurs,

switching is terminated and the SENSEFET remains off.

This causes Vcc to fall. When Vcc reaches the UVLO stop

voltage VSTOP (8 V), the protection is reset and the internal

high voltage current source charges the Vcc capacitor via the

Vstr pin. When Vcc reaches the UVLO start voltage VSTART

(12 V), the power switch resumes its normal operation. In

this manner, the auto−restart can alternately enable and

disable the switching of the power SENSEFET until the

fault condition is eliminated.

Over Load Protection (OLP)

Overload is defined as the load current exceeding

a pre−set level due to an unexpected event. In this situation,

the protection circuit should be activated in order to protect

the SMPS. However, even when the SMPS is operating

normally, the over load protection (OLP) circuit can be

activated during the load transition. In order to avoid this

undesired operation, the OLP circuit is designed to be

activated after a specified time to determine whether it is a

transient situation or an overload situation. In conjunction

with the Ipk current limit pin (if used) the current mode

feedback path would limit the current in the SENSEFET

when the maximum PWM duty cycle is attained. If the

output consumes more than this maximum power, the output

voltage (Vo) decreases below its rating voltage. This reduces

the current through the opto−coupler LED, which also

reduces the opto−coupler transistor current, thus increasing

the feedback voltage (VFB). If VFB exceeds 3 V, the

feedback input diode is blocked and the 5

mA current source

(IDELAY) starts to charge Cfb slowly up to Vcc. In this

condition, VFB increases until it reaches 6 V, when the

switching operation is terminated as shown in Figure 16.

The shutdown delay time is the time required to charge Cfb

from 3 V to 6 V with 5

mA current source.