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S71GS256 Datasheet(PDF) 132 Page - SPANSION |
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S71GS256 Datasheet(HTML) 132 Page - SPANSION |
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132 / 195 page  132 CellularRAM Type 2 cellRAM_00_A0 October 4, 2004 Advan ce In form ati o n Timing Diagrams Clock Period tCLK 12.5 15 ns CE# Setup to CLK Active Edge tCSP 45 ns Hold Time from Active CLK Edge tHD 22 ns Chip Disable to WAIT High-Z Output tHZ 88 ns CLK Rise or Fall Time tKHKL 1.6 1.6 ns Clock to WAIT Valid tKHTL 911 ns CLK HIGH or LOW Time tKP 33 ns Setup Time to Activate CLK Edge tSP 33 ns Figure 39. Initialization Period Table 35. Initialization Timing Parameters Parameter Symbol 70ns/80 MHz 85ns/66 MHz Units Notes MinMax MinMax Initialization Period (required before normal operations) tPU 150 150 µs Table 34. Burst WRITE Cycle Timing Requirements (Continued) Parameter Symbol 70ns/80 MHz 85ns/66 MHz Units Notes Min Max Min Max tPU VCC, VCCQ = 1.7V VCC (MIN) Device ready for normal operation |
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