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S71GS256 Datasheet(PDF) 129 Page - SPANSION |
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S71GS256 Datasheet(HTML) 129 Page - SPANSION |
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129 / 195 page  October 4, 2004 cellRAM_00_A0 CellularRAM Type 2 129 Ad vance Info rmat i o n Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. See “How Extended Timings Impact CellularRAM™ Operation” below. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a 4. 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 5. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. Table 31. Asynchronous READ Cycle Timing Requirements Parameter Symbol 85ns/66 MHz 70ns/80 MHz Units Notes MinMax MinMax Address Access Time tAA 85 70 ns ADV# Access Time tAADV 85 70 ns Page Access Time tAPA 25 20 ns Address Hold from ADV# HIGH tAVH 55 ns Address Setup to ADV# HIGH tAVS 10 10 ns LB#/UB# Access Time tBA 85 70 ns LB#/UB# Disable to DQ High-Z Output tBHZ 88 ns 4 LB#/UB# Enable to Low-Z Output tBLZ 10 10 ns 3 CE# HIGH between Subsequent Mixed-Mode Operations tCBPH 55 ns Maximum CE# Pulse Width tCEM 44 µs 2 CE# LOW to WAIT Valid tCEW 1 7.5 1 7.5 ns Chip Select Access Time tCO 85 70 ns CE# LOW to ADV# HIGH tCVS 10 10 ns Chip Disable to DQ and WAIT High-Z Output tHZ 88 ns 4 Chip Enable to Low-Z Output tLZ 10 10 ns 3 Output Enable to Valid Output tOE 20 20 ns Output Hold from Address Change tOH 55 ns Output Disable to DQ High-Z Output tOHZ 88 ns 4 Output Enable to Low-Z Output tOLZ 55 ns 3 Page Cycle Time tPC 25 20 ns READ Cycle Time tRC 85 70 ns ADV# Pulse Width LOW tVP 10 10 ns ADV# Pulse Width HIGH tVPH 10 10 ns |
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