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S71GS256 Datasheet(PDF) 128 Page - SPANSION |
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S71GS256 Datasheet(HTML) 128 Page - SPANSION |
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128 / 195 page  128 CellularRAM Type 2 cellRAM_00_A0 October 4, 2004 Advan ce In form ati o n AC Characteristics Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. Figure 37. AC Input/Output Reference Waveform Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). Figure 38. Output Load Circuit Table 30. Output Load Circuit VCCQR1/R2 1.8V 2.7K Ω Output Test Points Input (Note 1) VCCQ VSS VCCQ/2 (Note 2) VCCQ/2 (Note 3) DUT VCCQ R1 R2 30pF Test Point |
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