S71GS256 datasheet(130/195 Pages) SPANSION

130 / 195 page

130

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

Notes:

1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 38. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Figure 38. The Low-Z timings measure a 100mV

transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

Table 32. Burst READ Cycle Timing Requirements

Parameter

Symbol

70ns/80 MHz

85ns/66 MHz

Units

Notes

Min

Max

Min

Max

Burst to READ Access Time (Variable Latency)

tABA

CLK to Output Delay

tACLK

911

Address Setup to ADV# HIGH

tAVS

Burst OE# LOW to Output Delay

tBOE

CE# HIGH between Subsequent Mixed-Mode Operations

tCBPH

CE# LOW to WAIT Valid

tCEW

7.517.5

CLK Period

tCLK

12.5

CE# Setup Time to Active CLK Edge

tCSP

Hold Time from Active CLK Edge

tHD

Chip Disable to DQ and WAIT High-Z Output

tHZ

CLK Rise or Fall Time

tKHKL

1.6

CLK to WAIT Valid

tKHTL

911

CLK to DQ High-Z Output

tKHZ

3838

CLK to Low-Z Output

tKLZ

2525

Output HOLD from CLK

tKOH

CLK HIGH or LOW Time

tKP

Output Disable to DQ High-Z Output

tOHZ

Output Enable to Low-Z Output

tOLZ

Setup Time to Active CLK Edge

tSP

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