AD7745 datasheet(21/28 Pages) AD

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AD7745/AD7746

Rev. 0| Page 21 of 28

CAPDAC

The AD7745/AD7746 CDC full-scale input range is ±4.096 pF.

For simplicity of calculation, however, the following text and

diagrams use ±4 pF. The part can accept a higher capacitance

on the input and the common-mode or offset (not-changing

component) capacitance can be balanced by programmable

on-chip CAPDACs.

DATA

CDC

EXC

CIN(+)

CIN(–)

CAPDAC(+)

CAPDAC(–)

Figure 29. Using a CAPDAC

The CAPDAC can be understood as a negative capacitance

connected internally to the CIN pin. There are two independent

CAPDACs, one connected to the CIN(+) and the second

connected to the CIN(–). The relation between the capacitance

input and output data can be expressed as

(

) (

))

(

)

(

−

≈

CAPDAC

DATA

The CAPDACs have a 7-bit resolution, monotonic transfer

function, are well matched to each other, and have a defined

temperature coefficient. The CAPDAC full range (absolute

value) is not factory calibrated and can vary up to ±20% with

the manufacturing process. See the Specifications section and

typical performance characteristics in Figure 17.

The CAPDACs are shared by the two capacitive channels on the

AD7746. If the CAPDACs need to be set individually, the host

controller software should reload the CAPDAC values to the

AD7746 before executing conversion on a different channel.

SINGLE-ENDED CAPACITIVE INPUT

When configured for a single-ended mode (the CAPDIFF bit in

the Cap Setup register is set to 0), the AD7745/AD7746 CIN(–)

pin is disconnected internally. The CDC (without using the

CAPDACs) can measure only positive input capacitance in the

range of 0 pF to 4 pF (see Figure 30).

0x800000 ... 0xFFFFFF

DATA

CAPDIFF = 0

0 ... 4pF

CDC

EXC

CIN(+)

CIN(–)

0 ... 4pF

CAPDAC(+)

OFF

CAPDAC(–)

OFF

Figure 30. CDC Single-Ended Input Mode

The CAPDAC can be used for programmable shifting the input

range. The example in Figure 31 shows how to use the full

±4 pF CDC span to measure capacitance between 0 pF to 8 pF.

0x000000 ... 0xFFFFFF

DATA

CAPDIFF = 0

± 4pF

CDC

EXC

CIN(+)

CIN(–)

0 ... 8pF

CAPDAC(+)

4pF

CAPDAC(–)

0pF

Figure 31. Using CAPDAC in Single-Ended Mode

Figure 32 shows how to shift the input range further, up to

21 pF absolute value of capacitance connected to the CIN(+).

0x000000 ... 0xFFFFFF

DATA

CAPDIFF = 0

± 4pF

CDC

EXC

CIN(+)

CIN(–)

13 ... 21pF

(17

± 4pF)

CAPDAC(+)

17pF

CAPDAC(–)

0pF

Figure 32. Using CAPDAC in Single-Ended Mode

DIFFERENTIAL CAPACITIVE INPUT

When configured for a differential mode (the CAPDIFF bit in

the Cap Setup register set to 1), the AD7745/AD7746 CDC

measures the difference between positive and negative

capacitance input.

Each of the two input capacitances CX and CY between the EXC

and CIN pins must be less than 4 pF (without using the

CAPDACs) or must be less than 21 pF and balanced by the

CAPDACs. Balancing by the CAPDACs means that both

CX–CAPDAC(+) and CY–CAPDAC(–) are less than 4 pF.

If the unbalanced capacitance between the EXC and CIN pins is

higher than 4 pF, the CDC introduces a gain error, an offset

error, and nonlinearity error.

See the examples shown in Figure 33, Figure 34, and Figure 35.

0x000000 ... 0xFFFFFF

DATA

CAPDIFF = 1

± 4pF

CDC

EXC

CIN(+)

CIN(–)

0 ... 4pF

CAPDAC(+)

OFF

CAPDAC(–)

OFF

Figure 33. CDC Differential Input Mode

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