AD7745 datasheet(23/28 Pages) AD

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AD7745/AD7746

Rev. 0| Page 23 of 28

PARASITIC SERIAL RESISTANCE

DATA

CDC

EXC

RS1

CIN

RS2

Figure 39. Parasitic Serial Resistance

The AD7745/AD7746 CDC result is affected by a resistance in

series with the measured capacitance. The total serial resistance,

which refers to RS1 + RS2 on Figure 39, should be less than 1 kΩ

for the specified performance. See typical performance charac-

teristics shown in Figure 15.

CAPACITIVE GAIN CALIBRATION

The AD7745/AD7746 gain is factory calibrated for the full scale

of ±4.096 pF in the production for each part individually. The

factory gain coefficient is stored in a one-time programmable

(OTP) memory and is copied to the capacitive gain register at

power-up or after reset.

The gain can be changed by executing a capacitance gain

calibration mode, for which an external full-scale capacitance

needs to be connected to the capacitance input, or by writing a

user value to the capacitive gain register. This change would be

only temporary and the factory gain coefficient would be

reloaded back after power-up or reset. The part is tested and

specified only for use with the default factory calibration

coefficient.

CAPACITIVE SYSTEM OFFSET CALIBRATION

The capacitive offset is dominated by the parasitic offset in the

application, such as the initial capacitance of the sensor, any

parasitic capacitance of tracks on the board, and the capacitance

of any other connections between the sensor and the CDC.

Therefore, the AD7745/AD7746 are not factory calibrated for

capacitive offset. It is the user’s responsibility to calibrate the

system capacitance offset in the application.

Any offset in the capacitance input larger than ±1 pF should

first be removed using the on-chip CAPDACs. The small offset

within ±1 pF can then be removed by using the capacitance

offset calibration register.

One method of adjusting the offset is to connect a zero-scale

capacitance to the input and execute the capacitance offset

calibration mode. The calibration sets the midpoint of the

±4.096 pF range (that is, Output Code 0x800000) to that

zero-scale input.

Another method would be to calculate and write the offset cali-

bration register value, the LSB is value 31.25 aF (4.096 pF/217).

The offset calibration register is reloaded by the default value at

power-on or after reset. Therefore, if the offset calibration is not

repeated after each system power-up, the calibration coefficient

value should be stored by the host controller and reloaded as

part of the AD7745/AD7746 setup.

On the AD7746, the register is shared by the two capacitive

channels. If the capacitive channels need to be offset calibrated

individually, the host controller software should read the

AD7746 capacitive offset calibration register values after

performing the offset calibration on individual channels and

then reload the values back to the AD7746 before executing a

conversion on a different channel.

INTERNAL TEMPERATURE SENSOR

DIGITAL

FILTER

AND

SCALING

24-BIT

Σ-∆

MODULATOR

CLOCK

GENERATOR

INTERNAL TEMPERATURE SENSOR

VOLTAGE

REFERENCE

DATA

× I

∆V

VDD

Figure 40. Internal Temperature Sensor

The temperature sensing method used in the AD7745/AD7746

is to measure a difference in ∆VBE voltage of a transistor

operated at two different currents (see Figure 40). The ∆VBE

change with temperature is linear and can be expressed as

)

ln(

)

(

∆

where:

K is Boltzmann’s constant (1.38 × 10–23).

T is the absolute temperature in Kelvin.

q is the charge on the electron (1.6 × 10–19 coulombs).

N is the ratio of the two currents.

nf is the ideality factor of the thermal diode.

The AD7745/AD7746 uses an on-chip transistor to measure the

temperature of the silicon chip inside the package. The Σ-Δ

ADC converts the ∆VBE to digital, the data are scaled using

factory calibration coefficients, thus the output code is

proportional to temperature:

()

4096

2048

−

Code

Temperatur

The AD7745/AD7746 has a low power consumption resulting

in only a small effect due to the part self-heating (less than

0.5°C at VDD = 5 V).

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